XC3142A datasheet, PDF - EEWORLD Datasheet

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XC3142A: DescriptionLogic Cell Array Families; File Size45KB，8 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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XC3142A Overview

Logic Cell Array Families

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XC3100A

Logic Cell Array Families

Product Specifications

Features

• Ultra-high-speed FPGA family with six members

– 50-85 MHz system clock rates

– 190 to 325 MHz guaranteed flip-flop toggle rates

– 1.75 to 4.1 ns logic delays

• High-end additional family member in the 22 X 22

CLB array-size XC3195A device

• 8 mA output sink current and 8 mA source current

• Maximum power-down and quiescent current is 5 mA

• Both families are 100% architecture and pin-out

compatible with other XC3000 families

• Beyond this, XC3100A is also software and bitstream

compatible with the XC3000, XC3000A, and XC3000L

families

• 100% PCI complaint (A-2 speed grade in plastic quad

flat pack (PQFP) packaging).

XC3100A combines the features of the XC3000A and

XC3100 families.

• Additional interconnect resources for TBUFs and CE

inputs

• Error checking of the configuration bitstream

• Soft startup holds all outputs slew-rate limited during

initial power-up

• More advanced CMOS process

Description

The XC3100A is a performance-optimized relative of the

XC3000 and XC3000A families. While all families are

footprint compatible, XC3100A familiy extends the system

performance beyond 80 MHz.

The XC3100A familiy follows the XC4000 speed-grade

nomenclature, indicating device performance with a num-

ber that is based on the internal logic-block delay, in ns.

The XC3100A family offers the following enhancements

over the popular XC3100 family.

The XC3100A family has additional interconnect resources

to drive the I-inputs of TBUFs driving horizontal Longlines.

The CLB Clock Enable input can be driven from a second

vertical Longline. These two additions result in more

efficient and faster designs when horizontal Longlines are

used for data bussing.

During configuration, the XC3100A devices check the

bitstream format for stop bits in the appropriate positions.

Any error terminates the configuration and pulls INIT Low.

When the configuration process is finished and the device

starts up in user mode, the first activation of the outputs is

automatically slew-rate limited. This feature, called Soft

Startup, avoids the potential ground bounce when all

outputs are turned on simultaneously. After start-up, the

slew rate of the individual outputs is, as in all XC3000

families, determined by the individual configuration option.

The XC3100A family is a superset of the XC3000 families.

Any bitstream used to configure an XC3000, XC3000A,

XC3000L or XC3100 device, will configure the same-size

XC3100A device exactly the same way.

Device

XC3120A

XC3130A

XC3142A

XC3164A

XC3190A

XC3195A

CLBs

100

144

224

320

484

Array

8x8

10 x 10

12 x 12

16 x 14

16 x 20

22 x 22

User I/O

Max

120

144

176

Flip-Flops

256

360

480

688

928

1,320

Horizontal

Longlines

Configuration

Data Bits

14,779

22,176

30,784

46,064

64,160

94,944

2-177

XC3142A Related Products

	XC3142A	XC3195A	XC3190A	XC3164A	XC3100A
Description	Logic Cell Array Families	Logic Cell Array Families	Logic Cell Array Families	Logic Cell Array Families	Logic Cell Array Families

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