The UT54ACS165 and the UT54ACTS165 are 8-bit serial shift regis-
ters that, when clocked, shift the data toward serial output Q
H
. Parallel-
in access to each stage is provided by eight individual data inputs that
are enabled by a low level at the SH/LD input. The devices feature a
clock inhibit function and a complemented serial output Q
H
.
Clocking is accomplished by a low-to-high transition of the CLK input
while SH/LD is held high and CLK INH is held low. The functions of
the CLK and CLK INH (clock inhibit) inputs are interchangeable. Since
a low CLK input and a low-to-high transition of CLK INH will also
accomplish clocking, CLK INH should be changed to the high level
only while the CLK input is high. Parallel loading is disabled when
SH/LD is held high. Parallel inputs to the registers are enabled while
SH/LD is low independently of the levels of CLK, CLK INH or SER
inputs.
The devices are characterized over full military temperature range of
-55°C to +125°C.
PINOUTS
16-Pin DIP
Top View
SH/LD
CLK
E
F
G
H
Q
H
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
CLK INH
D
C
B
A
SER
Q
H
16-Lead Flatpack
Top View
SH/LD
CLK
E
F
G
H
Q
H
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
CLK INH
D
C
B
A
SER
Q
H
LOGIC SYMBOL
(1)
SH/LD
(15)
CLK INH
(2)
CLK
(10)
SER
(11)
A
(12)
B
(13)
C
(14)
D
(3)
E
(4)
F
(5)
G
(6)
H
SRG8
C1 (LOAD)
≥1
C2/
FUNCTION TABLE
INPUTS
SH/ CLK CLK SER PARALLEL
LD INH
A ... H
INTERNAL OUTPUTS
OUTPUTS
Q
A
Q
B
Q
H
Q
H
h
2D
1D
1D
L
H
H
H
H
X
L
L
L
H
X
L
↑
↑
X
X
H
L
X
a ... h
X
X
X
X
a
Q
A
H
L
Q
A
b
Q
B
Q
A
Q
A
Q
B
h
Q
H
Q
G
Q
G
Q
H
Q
H
Q
G
Q
G
Q
H
1
1D
(9)
Q
(7)
H
Q
H
X
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Note:
1. Q
n
= The state of the referenced output one setup time prior to the Low-to-
High clock transition.PINOUTS
LOGIC DIAGRAM
A
(11
)
SH/LD
B
(12)
C
(13)
D
(14)
E
(3)
F
(4)
G
(5)
H
(6)
(1)
CLK INH
CLK
(15)
(2)
S
C
SER
S
C
D Q
B
S
C
DQ
C
S
C
D Q
D
S
C
D Q
E
S
C
D Q
F
S
C
D Q
G
S
C
(9)
Q
H
(10
)
D
Q
A
(7)
D Q
H
R
R
R
R
R
R
R
R
Q
H
2
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
Θ
JC
I
I
P
D
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
20
±10
1
UNITS
V
V
°C
°C
°C
°C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
°C
3
DC ELECTRICAL CHARACTERISTICS
7
(V
DD
= 5.0V
±
10%; V
SS
= 0V
6
, -55°C < T
C
< +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
V
IL
PARAMETER
Low-level input voltage
1
ACTS
ACS
High-level input voltage
1
ACTS
ACS
Input leakage current
ACTS/ACS
Low-level output voltage
3
ACTS
ACS
High-level output voltage
3
ACTS
ACS
Short-circuit output current
2 ,4
ACTS/ACS
Output current
10
(Sink)
I
OH
Output current
10
(Source)
P
total
I
DDQ
ΔI
DDQ
Power dissipation
2, 8, 9
Quiescent Supply Current
Quiescent Supply Current Delta
ACTS
V
IN
= V
DD
or V
SS
I
OL
= 8.0mA
I
OL
= 100μA
I
OH
= -8.0mA
I
OH
= -100μA
V
O
= V
DD
and V
SS
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
IN
= V
DD
or V
SS
V
OH
= V
DD
- 0.4V
C
L
= 50pF
V
DD
= 5.5V
For input under test
V
IN
= V
DD
- 2.1V
For all other inputs
V
IN
= V
DD
or V
SS
V
DD
= 5.5V
C
IN
C
OUT
Input capacitance
5
Output capacitance
5
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
15
15
pF
pF
2.9
10
1.6
mW/
MHz
μA
mA
-8
mA
.7V
DD
V
DD
- 0.25
-200
8
200
.5V
DD
.7V
DD
-1
1
CONDITION
MIN
MAX
0.8
.3V
DD
UNIT
V
V
IH
V
I
IN
V
OL
μA
0.40
0.25
V
V
OH
V
I
OS
I
OL
mA
mA
4
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
≤
5.0E5 amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose
≤
1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
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