Subscriber Line) system by providing all of the active
analog circuitry needed to connect an HDSL digital
signal processor to an external compromise hybrid and
a HDSL line transformer. The transmit and receive
filter responses automatically change with clock fre-
quency—allowing the AFE1115 to operate over a
range of data rates from 196kbps to 1.168Mbps.
Functionally, this unit consists of a transmit and a
receive section with a VCXO (Voltage Controlled
vcDATA
vcSCLK
vcLE
VCXO
DAC
Oscillator
Crystal Oscillator) control DAC and VCXO circuitry.
The transmit section generates, filters, and buffers
outgoing 2B1Q data. The receive section filters and
digitizes the symbol data received on the telephone
line. Data to the VCXO and symbol data are sent to the
AFE1115 via two serial interfaces; the receive data is
available as a 14-bit parallel word. This IC operates on
a single 5V supply. The digital circuitry in the unit can
be connected to a supply from 3.3V to 5V. It is housed
in a small 56-pin SSOP package.
vcDAC
VCXO Output
VCXO Input
VCXO Output Clock
Pulse
Former
Filter
Output
Buffer
txLINE+
txLINE–
PLL
OUT
PLL
IN
txDATA+
txSCLK
txCLK
rxSYNC
rxLOOP
2
rxGAIN
Delta-Sigma
Modulator
14
rxDATA
Decimation
Filter
Receive
Control
Transmit
Control
Voltage
Reference
REF
P
V
CM
REF
N
rxLINE+
rxLINE–
rxHYB+
rxHYB–
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
NOTES: (1) With a balanced differential signal, the positive input is 180° out of phase with the negative input, therefore the actual voltage swing about the common-
mode voltage on each pin is
±1.5V
to achieve a total input range of
±3.0V
or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the symbol
rate with interpolated values. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (16.5dBm output from txLINEP
and txLINEN). (5) See the Test Method section of this data sheet for more information. (6) Guaranteed by design and characterization. (7) Uncancelled Echo is a
measure of the total analog errors in the transmitter and receiver sections including the effect of non-linearity and noise. See the Discussion of Specifications sections
of this data sheet for more information. (8) Power dissipation includes only the power dissipated with in the component and does not include power dissipated in the
external loads. See the Discussion of Specifications section for more information.
®
AFE1115
2
PIN CONFIGURATION
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
(1)
346
TEMPERATURE
RANGE
–40°C to +85°C
PRODUCT
PACKAGE
56-Pin Plastic SSOP
vcOUT
vcINP
vcCLK
DVDD
Unused Pin
Unused Pin
txCLK
txSCLK
txDATA
rxDATA0
rxDATA1
rxDATA2
rxDATA3
rxDATA4
rxDATA5
GNDD
DV
DD
rxDATA6
rxDATA7
rxDATA8
rxDATA9
rxDATA10
rxDATA11
rxDATA12
rxDATA13
Unused Pin
rxSYNC
rxGAIN0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
AFE1115E
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
DGND
AFE1115E
vcSCLK
vcDATA
vcLATCH
PLL
IN
PLL
OUT
AV
DD
AGND
AGND
vcDAC
AGND
txLINE+
AV
DD
txLINE–
AGND
AV
DD
vrREF
V
CM
vrREF
AGND
AGND
rxLINE+
rxLINE–
rxHYB+
rxHYB–
AV
DD
rxLOOP
rxGAIN1
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
®
3
AFE1115
PIN DESCRIPTIONS
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
TYPE
Output
Input
Output
Power
NC
NC
Input
Input
Input
Output
Output
Output
Output
Output
Output
Ground
Power
Output
Output
Output
Output
Output
Output
Output
Output
NC
Input
Input
Input
Input
Power
Input
Input
Input
Input
Ground
Ground
Output
Output
Output
Power
Ground
Output
Power
Output
Ground
Output
Ground
Ground
Power
Output
Input
Input
Input
Input
Ground
NAME
vcOUT
vcINP
vcCLK
DVDD
Unused Pin
Unused Pin
txCLK
txSCLK
txDATA
rxDATA0
rxDATA1
rxDATA2
rxDATA3
rxDATA4
rxDATA5
GNDD
DV
DD
rxDATA6
rxDATA7
rxDATA8
rxDATA9
rxDATA10
rxDATA11
rxDATA12
rxDATA13
Unused Pin
rxSYNC
rxGAIN0
rxGAIN1
rxLOOP
AV
DD
rxHYB–
rxHYB+
rxLINE–
rxLINE+
AGND
AGND
vrREFP
V
CM
vrREFN
AV
DD
AGND
txLINE–
AV
DD
txLINE+
AGND
vcDAC
AGND
AGND
AV
DD
PLL
OUT
PLL
IN
vcLATCH
vcDATA
vcSCLK
DGND
DESCRIPTION
VCXO Output
VCXO Input
VCXO Output Clock
Digital Supply (+3.3 to +5V)
Transmit Baud Clock (XMTLE signal) (1168kHz for E1)
Transmit Serial Clock
Transmit Data Input
ADC Output Bit-0
ADC Output Bit-1
ADC Output Bit-2
ADC Output Bit-3
ADC Output Bit-4
ADC Output Bit-5
Digital Ground
Digital Supply (+3.3 to +5V)
ADC Output Bit-6
ADC Output Bit-7
ADC Output Bit-8
ADC Output Bit-9
ADC Output Bit-10
ADC Output Bit-11
ADC Output Bit-12
ADC Output Bit-13
(DV
DD
may be connected for pinout compatibility with AFE1105)
ADC Sync Signal (392kHz for T1, 584kHz for E1)
Receive Gain Control Bit-0
Receive Gain Control Bit-1
Loopback Control Signal (loopback is enabled by positive signal)
Analog Supply (+5V)
Negative Input from Hybrid Network
Positive Input from Hybrid Network
Negative Line Input
Positive Line Input
Analog Ground
Analog Ground
Positive Reference Output
Common-mode Voltage (buffered)
Negative Reference Output
Analog Supply (+5V)
Analog Ground
Negative Line Output
Analog Supply (+5V)
Positive Line Output
Analog Ground
VCXO Control
Analog Ground
PLL Ground
PLL Supply
PLL Filter Output
PLL Filter Input
VCXO Control Latch Enable
VCXO Control Data
VCXO Control Serial Clock
Digital Ground
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
AFE1115
4
TYPICAL PERFORMANCE CURVES
At Output of Pulse Transformer
The curves shown below are measured at the line output of the HDSL transformer. Typical at 25°C, AV
DD
= +5V, DV
DD
= +3.3V, unless otherwise specified.
POWER SPECTRAL DENSITY LIMIT
–20
Power Spectral Density (dBm/Hz)
–38dBm/Hz for T1
–40
–40dBm/Hz for E1
–60
–80dB/decade
T1
E1
–118dBm/Hz
for T1
–120dBm/Hz
for E1
–80
196kHz
–100
292kHz
–120
1K
10K
100K
Frequency (Hz)
1M
10M
CURVE 1. Upper Bound of Power Spectral Density Measured at Output of HDSL Transformer.
0.4T 0.4T
B = 1.07
C = 1.00
D = 0.93
NORMALIZED
LEVEL
A
B
C
D
E
F
G
H
0.01
1.07
1.00
0.93
0.03
–0.01
–0.16
–0.05
QUATERNARY SYMBOLS
+3
0.0264
2.8248
2.6400
2.4552
0.0792
–0.0264
–0.4224
–0.1320
+1
0.0088
0.9416
0.8800
0.8184
0.0264
–0.0088
–0.1408
–0.0440
–1
–0.0088
–0.9416
–0.8800
–0.8184
–0.0264
0.0088
0.1408
0.0440
–3
–0.0264
–2.8248
–2.6400
–2.4552
–0.0792
0.0264
0.4224
0.1320
DON'T DELETE TABLE
UNTIL KNOWN IF TEEPLE IS LEAVING IT IN?
1.25T
A = 0.01
F = –0.01
–1.2T
–0.6T
0.5T
E = 0.03
H = –0.05
14T
A = 0.01
F = –0.01
50T
G = –0.16
CURVE 2. Transmitted Pulse Template and Actual Performance as Measured at Transformer Output.
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