DISCRETE SEMICONDUCTORS
DATA SHEET
BST82
N-channel enhancement mode
vertical D-MOS transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
DESCRIPTION
N-channel enhancement mode
vertical D-MOS transistor in SOT23
envelope and designed for use as
Surface Mounted Device (SMD) in
thin and thick-film circuits for
telephone ringer and for application
with relay, high-speed and
line-transformer drivers.
FEATURES
•
Direct interface to C-MOS, TTL,
etc.
•
High-speed switching
•
No second breakdown
•
Low R
DS(on)
Transfer admittance
I
D
= 175 mA; V
DS
= 5 V
PINNING - SOT23
1
2
3
PIN CONFIGURATION
= gate
= source
= drain
Y
fs
typ.
QUICK REFERENCE DATA
Drain-source voltage
Drain-source voltage (non-repetitive peak;
t
p
≤
2 ms)
Gate-source voltage (open drain)
Drain current (DC)
Total power dissipation up to T
amb
= 25
°C
Drain-source ON-resistance
I
D
= 150 mA; V
GS
= 5 V
R
DS(on)
typ.
max.
V
DS
V
DS(SM)
±V
GSO
I
D
P
tot
max.
max.
max.
max.
max.
BST82
80 V
100 V
20 V
175 mA
300 mW
7
Ω
10
Ω
150 mS
handbook, halfpage
3
handbook, 2 columns
d
g
1
Top view
2
MSB003
MBB076 - 1
s
Marking: 02p
Fig.1 Simplified outline and symbol.
April 1995
2
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Drain-source voltage
Drain-source voltage (non-repetitive peak; t
p
≤
2 ms)
Gate-source voltage (open drain)
Drain current (DC)
Drain current (peak)
Total power dissipation up to T
amb
= 25
°C
(note 1)
Storage temperature range
Junction temperature
THERMAL RESISTANCE
From junction to ambient (note 1)
Note
1. Transistors mounted on a ceramic substrate of 7 mm x 5 mm x 0.7 mm.
R
th j-a
=
V
DS
V
DS(SM)
±V
GSO
I
D
I
DM
P
tot
T
stg
T
j
max.
max.
max.
max.
max.
max.
max.
80 V
100 V
20 V
BST82
175 mA
600 mA
300 mW
150
°C
−65
to + 150
°C
430 K/W
April 1995
3
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
CHARACTERISTICS
T
j
= 25
°C
unless otherwise specified
Drain-source breakdown voltage
I
D
= 10
µA;
V
GS
= 0
Drain-source leakage current
V
DS
= 60 V; V
GS
= 0
Gate-source leakage current
V
GS
= 20 V; V
DS
= 0
Gate-source cut-off voltage
I
D
= 1 mA; V
DS
= V
GS
Drain-source ON-resistance
I
D
= 150 mA; V
GS
= 5 V
Transfer admittance
I
D
= 175 mA; V
DS
= 5 V
Input capacitance at f = 1 MHz
V
DS
= 10 V; V
GS
= 0
Output capacitance at f = 1 MHz
V
DS
= 10 V; V
GS
= 0
Feedback capacitance at f = 1 MHz
V
DS
= 10 V; V
GS
= 0
Switching times (see Figs 2 and 3)
I
D
= 175 mA; V
DD
= 50 V; V
GS
= 0 to 10 V
t
on
typ.
max.
typ.
max.
4 ns
10 ns
4 ns
10 ns
C
rss
typ.
max.
3 pF
6 pF
C
oss
typ.
max.
13 pF
20 pF
C
iss
typ.
max.
15 pF
30 pF
Y
fs
typ.
150 mS
R
DS(on)
typ.
max.
V
(P)GS
min.
max.
1.5 V
3.5 V
7
Ω
10
Ω
I
GSS
max.
100 nA
I
DSS
max.
1.0
µA
V
(BR)DSS
min.
80 V
BST82
t
off
April 1995
4
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BST82
handbook, halfpage
VDD = 50 V
handbook, halfpage
90 %
INPUT
10 %
10 V
0V
ID
50
Ω
MSA631
90 %
OUTPUT
10 %
ton
toff
MBB692
Fig.2 Switching times test circuit.
Fig.3 Input and output waveforms.
10
3
handbook, halfpage
ID
(mA)
MDA762
VGS = 10 V
8V
6V
5V
handbook, halfpage
1
MDA732
ID
VDS = 10 V
5V
(A)
0.8
0.6
10
2
0.4
0.2
10
0
2
4
6
8
10
RDSon (Ω)
0
0
2
4
6
8
10
VGS (V)
Fig.4 T
j
= 25
°C;
typical values.
Fig.5 T
j
= 25
°C;
typical values.
April 1995
5
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