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5962F9672401VXC

Description
DUAL 4-BIT DRIVER, TRUE OUTPUT, CERAMIC, FP-20
Categorylogic    logic   
File Size44KB,4 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Download Datasheet Parametric Compare View All

5962F9672401VXC Overview

DUAL 4-BIT DRIVER, TRUE OUTPUT, CERAMIC, FP-20

5962F9672401VXC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerRenesas Electronics Corporation
Parts packaging codeDFP
package instructionDFP, FL20,.3
Contacts20
Reach Compliance Codenot_compliant
seriesACT
JESD-30 codeR-CDFP-F20
JESD-609 codee0
Load capacitance (CL)50 pF
Logic integrated circuit typeBUS DRIVER
MaximumI(ol)0.008 A
Number of digits8
Number of functions1
Number of ports2
Number of terminals20
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Encapsulate equivalent codeFL20,.3
Package shapeRECTANGULAR
Package formFLATPACK
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Prop。Delay @ Nom-Sup17 ns
propagation delay (tpd)17 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class V
Maximum seat height2.92 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
total dose300k Rad(Si) V
width6.92 mm
ACS573MS
January 1996
Radiation Hardened Octal
Three-State Transparent Latch
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR,
CDIP2-T20, LEAD FINISH C
TOP VIEW
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96724 and Intersil’s QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
2
/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability . . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current
1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 17ns (Max), 12ns (Typ)
GND 10
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR,
CDFP4-F20, LEAD FINISH C
TOP VIEW
Description
OE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
The Intersil ACS573MS is a Radiation Hardened Octal Transparent
Latch with an active low output enable. The outputs are transparent to
the inputs when the latch enable (LE) is High. When the latch goes low
the data is latched. The output enable controls the three-state outputs.
When the output enable pins (OE) are high the output is in a high
impedance state. The latch operation is independent of the state of
output enable.
The ACS573MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic family.
The ACS573MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or a
D0
D1
D2
D3
D4
D5
D6
D7
GND
Ordering Information
PART NUMBER
5962F9672401VRC
5962F9672401VXC
ACS573D/Sample
ACS573K/Sample
ACS573HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
25
o
C
25
o
C
25
o
C
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Spec Number
1
518893
File Number
4093

5962F9672401VXC Related Products

5962F9672401VXC 5962F9672401VRC
Description DUAL 4-BIT DRIVER, TRUE OUTPUT, CERAMIC, FP-20 DUAL 4-BIT DRIVER, TRUE OUTPUT, SIDE BRAZED, DIP-20
Is it Rohs certified? incompatible incompatible
Maker Renesas Electronics Corporation Renesas Electronics Corporation
Parts packaging code DFP DIP
package instruction DFP, FL20,.3 CERAMIC, DIP-20
Contacts 20 20
Reach Compliance Code not_compliant not_compliant
series ACT ACT
JESD-30 code R-CDFP-F20 R-CDIP-T20
JESD-609 code e0 e0
Load capacitance (CL) 50 pF 50 pF
Logic integrated circuit type BUS DRIVER BUS DRIVER
MaximumI(ol) 0.008 A 0.008 A
Number of digits 8 8
Number of functions 1 1
Number of ports 2 2
Number of terminals 20 20
Maximum operating temperature 125 °C 125 °C
Minimum operating temperature -55 °C -55 °C
Output characteristics 3-STATE 3-STATE
Output polarity TRUE TRUE
Package body material CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
encapsulated code DFP DIP
Encapsulate equivalent code FL20,.3 DIP20,.3
Package shape RECTANGULAR RECTANGULAR
Package form FLATPACK IN-LINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED
power supply 5 V 5 V
Prop。Delay @ Nom-Sup 17 ns 17 ns
propagation delay (tpd) 17 ns 17 ns
Certification status Not Qualified Not Qualified
Filter level MIL-PRF-38535 Class V MIL-PRF-38535 Class V
Maximum seat height 2.92 mm 5.08 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V
surface mount YES NO
technology CMOS CMOS
Temperature level MILITARY MILITARY
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form FLAT THROUGH-HOLE
Terminal pitch 1.27 mm 2.54 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
total dose 300k Rad(Si) V 300k Rad(Si) V
width 6.92 mm 7.62 mm
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