HYB 39S256400/800/160T
256-MBit Synchronous DRAM
256-MBit Synchronous DRAM
• High Performance:
• Multiple Burst Read with Single Write
Operation
-8A
125
8
6
12
6
-8B
100
10
6
15
7
Units
MHz
ns
ns
ns
ns
• Automatic and Controlled Precharge
Command
• Data Mask for Read/Write Control (x4, x8)
• Data Mask for Byte Control (x16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• 8192 Refresh Cycles / 64 ms (7.8
µs)
• Random Column Address every CLK
(1-N Rule)
• Single 3.3 V
±
0.3 V Power Supply
• LVTTL Interface
• Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
• -7.5
-8
-8A
-8B
parts
parts
parts
parts
for PC133 3-3-3 operation
for PC100 2-2-2 operation
for PC100 3-2-2 operation
for PC100 3-2-3 operation
-7.5
-8
125
8
6
10
6
f
CK
t
CK3
t
AC3
t
CK2
t
AC2
133
7.5
5.4
12
6
• Fully Synchronous to Positive Clock Edge
• 0 to 70
°C
operating temperature
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2 & 3
• Programmable Wrap Sequence: Sequential
or Interleave
• Programmable Burst Length: 1, 2, 4, 8
The HYB 39S256400/800/160T are four bank Synchronous DRAM’s organized as
4 banks
×
16MBit x4, 4 banks
×
8MBit x8 and 4 banks
×
4Mbit x16 respectively. These synchro-
nous devices achieve high speed data transfer rates for CAS-latencies by employing a chip
architecture that prefetches multiple bits and then synchronizes the output data to a system clock.
The chip is fabricated using the Infineon advanced 256 MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3 V
±
0.3 V power supply and are available in TSOPII packages.
Data Book
1
12.99
HYB 39S256400/800/160T
256-MBit Synchronous DRAM
Ordering Information
Type
HYB 39S256400T-7.5
HYB 39S256400T-8
HYB 39S256400T-8A
HYB 39S256400T-8B
HYB 39S256800T-7.5
HYB 39S256800T-8
HYB 39S256800T-8A
HYB 39S256800T-8B
HYB 39S256160T-7.5
HYB 39S256160T-8
HYB 39S256160T-8A
HYB 39S256160T-8B
Ordering Code Package
Description
PC133-333-520 P-TSOP-54-2 (400mil) 133 MHz 4B
×
16M x4 SDRAM
PC100-222-620 P-TSOP-54-2 (400mil) 125 MHz 4B
×
16M x4 SDRAM
PC100-322-620 P-TSOP-54-2 (400mil) 125 MHz 4B
×
16M x4 SDRAM
PC100-323-620 P-TSOP-54-2 (400mil) 100 MHz 4B
×
16M x4 SDRAM
PC133-333-520 P-TSOP-54-2 (400mil) 133 MHz 4B
×
8M x8 SDRAM
PC100-222-620 P-TSOP-54-2 (400mil) 125 MHz 4B
×
8M x8 SDRAM
PC100-322-620 P-TSOP-54-2 (400mil) 125 MHz 4B
×
8M x8 SDRAM
PC100-323-620 P-TSOP-54-2 (400mil) 100 MHz 4B
×
8M x8 SDRAM
PC133-333-520 P-TSOP-54-2 (400mil) 133 MHz 4B
×
4M x16 SDRAM
PC100-222-620 P-TSOP-54-2 (400mil) 125 MHz 4B
×
4M x16 SDRAM
PC100-322-620 P-TSOP-54-2 (400mil) 125 MHz 4B
×
4M x16 SDRAM
PC100-323-620 P-TSOP-54-2 (400mil) 100 MHz 4B
×
4M x16 SDRAM
Pin Definitions and Functions
CLK
CKE
CS
RAS
CAS
WE
A0 - A12
BA0, BA1
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
DQ
DQM, LDQM,
UDQM
Data Input/Output
Data Mask
Power (+ 3.3 V)
Ground
Power for DQ’s (+ 3.3 V)
Ground for DQ’s
Not connected
V
DD
V
SS
V
DDQ
V
SSQ
N.C.
Data Book
2
12.99
HYB 39S256400/800/160T
256-MBit Synchronous DRAM
Functional Block Diagrams
Column Addresses
A0 - A9, A11, AP,
BA0, BA1
Row Addresses
A0 - A12,
BA0, BA1
Column Address
Counter
Column Address
Buffer
Row Address
Buffer
Refresh Counter
Row
Decoder
Row
Decoder
Row
Decoder
Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Column Decoder
Sense amplifier & I(O) Bus
Column Decoder
Sense amplifier & I(O) Bus
Bank 0
8196
x 2048
x 4 Bit
Bank 1
8196
x 2048
x 4 Bit
Bank 2
8196
x 2048
x 4 Bit
Column Decoder
Sense amplifier & I(O) Bus
Memory
Array
Memory
Array
Memory
Array
Memory
Array
Bank 3
8196
x 2048
x 4 Bit
Input Buffer
Output Buffer
Control Logic &
Timing Generator
DQ0 - DQ3
Block Diagram: 64M
×
4 SDRAM (13 / 11 / 2 addressing)
Data Book
4
CLK
CKE
CS
RAS
CAS
WE
DQM
SPB04127
12.99
Creative Market
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