64K x 32
CMOS Static RAM Module
Features
High-density 2MB Static RAM module
Low profile 64-pin ZIP (Zig-zag In-line vertical Package) or 64-
pin SIMM (Single In-line Memory Module)
Ultra fast access time: 12ns (max.)
Surface mounted plastic components on an epoxy laminate
(FR-4) substrate
Single 5V (±10%) power supply
Multiple GND pins and decoupling capacitors for maximum
noise immunity
Inputs/outputs directly TTL-compatible
IDT7MP4036
x
x
Description
The IDT7MP4036 is a 64K x 32 Static RAM module constructed on
an epoxy laminate (FR-4) substrate using eight 64K x 4 Static RAMs in
plastic SOJ packages. Availability of four chip select lines (one for each
group of two RAMs) provides byte access. Extremely fast speeds can be
achieved due to the use of 256K Static RAMs fabricated in IDT’s high-
performance, high-reliability CMOS technology. The IDT7MP4036 is
available with access time as fast as 12ns with minimal power consumption.
The IDT7MP4036 is packaged in a 64-pin FR-4 ZIP (Zig-zag In-line
vertical Package)or a 64-pin SIMM (Single In-line Memory Module). The
ZIP configuration allows 64 pins to be placed on a package 3.65 inches
long and 0.35 inches wide. At only 0.50 inches high, this low-profile
package is ideal for systems with minimum board spacing, while the SIMM
configuration allows use of edge mounted sockets to secure the module.
All inputs and outputs of the IDT7MP4036 are TTL-compatible and
operate from a single 5V supply. Full asynchronous circuitry requires no
clocks or refresh for operation and provides equal access and cycle times
for ease of use.
Two identification pins (PD
0
and PD
1
) are provided for applications in
which different density versions of the module are used. In this way, the
target system can read the respective levels of PD
0
and PD
1
to determine
a 64K depth.
x
x
x
x
x
Pin Configuration
(1)
1
PD
0
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
14
CS
1
CS
3
NC
GND
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
GND
PD
1
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
15
GND
A
15
CS
2
CS
4
NC
OE
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
PD
0
– OPEN
PD
1
– GND
,
Pin Names
I/O
0-31
A
0-15
CS
1-4
WE
OE
PD
0-1
V
CC
GND
NC
Data Inputs/Outputs
Addresses
Chip Selects
Write Enable
Output Enable
Depth Identification
Power
Ground
No Connect
2682 tbl 01
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
2682 drw 02
ZIP, SIMM
Top View
NOTE:
1. Pins 2 and 3 (PD
0
and PD
1
) are read by the user to determine the density of
the module. If PD
0
reads Open and PD
1
reads GND, then the module had a
64K depth.
DECEMBER 1999
1
DSC-2682/6
©1999 Integrated Device Technology, Inc.
IDT7MP4036
64K x 32 CMOS Static RAM Module
Commercial Temperature Ranges
Functional Block Diagram
CS
1
ADDRESS
WE
OE
8
8
8
8
2682 drw 01
Truth Table
Mode
2
CS
2
CS
3
CS
4
CS
H
L
L
L
OE
X
L
H
X
WE
X
H
H
L
Output
High-Z
D
OUT
High-Z
D
IN
Power
Standby
Active
Active
Active
2682 tbl 05
PD
0-1
Standby
Read
16
64K x 32
RAM
Read
,
Write
I/O
0-31
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect to GND
Operating Temperature
Temperature
Under Bias
Storage Temperature
DC Output Current
Commercial
-0.5 to +7.0
0 to +70
-10 to +85
-55 to +125
50
Unit
V
°C
°C
°C
mA
2682 tbl 06
Capacitance
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN(D)
C
IN(A)
C
OUT
Parameter
Input Capacitance (Data)
Input Capacitance
(Address & Control)
Output Capacitance
Conditions
V
IN
= 0V
V
IN
= 0V
V
OUT
= 0V
Typ.
15
70
15
Unit
pF
pF
pF
2682 tbl 02
T
A
T
BIAS
T
STG
I
OUT
NOTE:
1. This parameter is guaranteed by design but not tested.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. I/O pins must not exceed V
CC
+0.5V.
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
(2)
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
Max.
5.5
0
6.0
0.8
Unit
V
V
V
V
2682 tbl 03
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Ambient
Temperature
0°C to +70°C
GND
0V
VCC
5V ± 10%
2682 tbl 04
____
NOTES:
1. V
IL
(min) = –1.5V for pulse width less than 10ns.
2. I/O pins must not exceed V
CC
+0.5V.
2
IDT7MP4036
64K x 32 CMOS Static RAM Module
Commercial Temperature Ranges
DC Electrical Characteristics
(V
CC
= 5.0V ±10%, T
A
= 0°C to +70°C)
Symbol
II
LI
I
II
LI
I
II
LO
I
V
OL
V
OH
I
CC
I
SB
I
SB1
Parameter
Input Leakage Current
(Address and Control)
Input Leakage Current
(Data)
Output Leakage Current
Output Low Voltage
Output High Voltage
Dynamic Operating
Current
Standby Supply
Current
Full Standby
Supply Current
Test Condition
V
CC
= Max., V
IN
= GND to V
CC
V
CC
= Max., V
IN
= GND to V
CC
V
CC
= Max.,
CS
= V
IH
, V
OUT
= GND to V
CC
I
OL
= 8mA, V
CC
= Min.
I
OH
= -4mA, V
CC
= Min.
V
CC
= Max.,
CS
= V
IL
,
f = f
MAX
, Outputs Open
V
CC
= Max.,
CS
> V
IH
,
f = f
MAX
, Outputs Open
CS
> V
CC
- 0.2V, f = 0
V
IN
> V
CC
- 0.2V or < 0.2V
Min.
____
Max.
80
10
10
0.4
____
Unit
µA
µA
µA
V
V
mA
mA
mA
2682 tbl 07
____
____
____
2.4
____
1280
360
240
____
____
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2682 tbl 08
+5V
+5V
480Ω
480Ω
DATA
OUT
DATA
OUT
5pF
*
255Ω
30pF*
255Ω
2682 drw 03
,
*incluces scope and jig.
2682 drw 04
,
Figure 1. Output Load
Figure 2. Output Load
(for t
OLZ
, t
OHZ
, t
CHZ
, t
CLZ
, t
WHZ
, t
OW
)
6.42
3
IDT7MP4036
64K x 32 CMOS Static RAM Module
Commercial Temperature Ranges
AC Electrical Characteristics
(V
CC
= 5V ±10%, T
A
= 0°C to +70°C)
7MP4036SxxZ, 7MP4036SxxM
-12
(2)
Symbol
Parameter
Min.
Max.
Min.
-13
Max.
Min.
-15
Max.
Unit
Read Cycle
t
RC
t
AA
t
ACS
t
CLZ
(1)
t
OE
t
OLZ
(1)
t
CHZ
(1)
t
OHZ
(1)
t
OH
t
PU
(1)
t
PD
(1)
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Deselect to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power-Down Time
12
____
____
____
13
____
____
____
15
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
12
____
13
13
____
15
15
____
2
____
2
____
2
____
7
____
8
____
9
____
0
____
0
____
0
____
7
7
____
7
7
____
8
8
____
____
____
____
3
0
____
3
0
____
3
0
____
____
____
____
12
13
15
Write Cycle
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
(1)
t
DW
t
DH
t
OW
(1)
Write Cycle Time
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write Enable to Output in High-Z
Data to Write Time Overlap
Data Hold Time
Output Active from End-of-Write
12
10
11
1
10
0
____
____
____
____
____
____
____
13
11
12
1
11
0
____
____
____
____
____
____
____
15
12
13
1
12
0
____
____
____
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2682 tbl 09
7
____
7
____
8
____
7
1
2
7
1
2
8
1
1
____
____
____
____
____
____
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only.
4
IDT7MP4036
64K x 32 CMOS Static RAM Module
Commercial Temperature Ranges
AC Electrical Characteristics
(V
CC
= 5V ±10%, T
A
= 0°C to +70°C)
7MP4036SxxZ, 7MP4036SxxM
-20
Symbol
Parameter
Min.
Max.
Min.
-25
Max.
Min.
-35
Max.
Unit
Read Cycle
t
RC
t
AA
t
ACS
t
CLZ
(1)
t
OE
t
OLZ
(1)
t
CHZ
(1)
t
OHZ
(1)
t
OH
t
PU
(1)
t
PD
(1)
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Deselect to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power-Down Time
20
____
____
25
____
____
35
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
____
25
25
____
35
35
____
____
____
____
3
____
3
____
3
____
10
____
12
____
25
____
0
____
0
____
0
____
10
10
____
15
15
____
22
22
____
____
____
____
3
0
____
3
0
____
3
0
____
____
____
____
20
25
35
Write Cycle
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
(1)
t
DW
t
DH
t
OW
(1)
Write Cycle Time
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write Enable to Output in High-Z
Data to Write Time Overlap
Data Hold Time
Output Active from End-of-Write
20
15
15
0
15
0
____
____
25
20
20
0
20
0
____
____
35
30
30
0
30
0
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2682 tbl 10
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
12
____
____
15
____
____
18
____
____
12
0
0
15
0
0
20
0
0
____
____
____
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only.
6.42
5
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