SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
D
D
D
’ALS174
and
’AS174
Contain Six Flip-Flops
With Single-Rail Outputs
’ALS175
and ’AS175B Contain Four
Flip-Flops With Double-Rail Outputs
Buffered Clock and Direct-Clear Inputs
D
D
Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
Fully Buffered Outputs for Maximum
Isolation From External Disturbances
(’AS Only)
SN54ALS174 . . . J OR W PACKAGE
SN54AS174 . . . J PACKAGE
SN74ALS174, SN74AS174 . . . D , N, OR NS PACKAGE
(TOP VIEW)
SN54ALS175 . . . J OR W PACKAGE
SN54AS175B . . . J PACKAGE
SN74ALS175, SN74AS175B . . . D, N, OR NS PACKAGE
(TOP VIEW)
CLR
1Q
1D
2D
2Q
3D
3Q
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
6Q
6D
5D
5Q
4D
4Q
CLK
CLR
1Q
1Q
1D
2D
2Q
2Q
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
4Q
4Q
4D
3D
3Q
3Q
CLK
SN54ALS174, SN54AS174 . . . FK PACKAGE
(TOP VIEW)
SN54ALS175 . . . FK PACKAGE
(TOP VIEW)
1Q
CLR
NC
V
CC
6Q
1D
2D
NC
2Q
3D
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
6D
5D
NC
5Q
4D
1Q
1D
NC
2D
2Q
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1Q
CLR
NC
V
CC
4Q
4Q
4D
NC
3D
3Q
3Q
GND
NC
CLK
4Q
NC – No internal connection
description
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a
direct-clear (CLR) input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly
related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low
level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
2Q
GND
NC
CLK
3Q
1
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
SN74ALS174N
PDIP – N
Tube
SN74AS174N
SN74ALS175N
SN74AS175BN
Tube
Tape and reel
Tube
0°C to 70°C
SOIC – D
Tape and reel
Tube
Tape and reel
Tube
Tape and reel
SN74ALS174D
SN74ALS174DR
SN74AS174D
SN74AS174DR
SN74ALS175D
SN74ALS175DR
SN74AS175BD
SN74AS175BDR
SN74ALS174NSR
SOP – NS
Tape and reel
SN74AS174NSR
SN74ALS175NSR
SN74AS175BNSR
SNJ54ALS174J
CDIP – J
Tube
SNJ54AS174J
SNJ54ALS175J
SNJ54AS175BJ
–55°C to 125°C
CFP – W
Tube
SNJ54ALS174W
SNJ54ALS175W
SNJ54ALS174FK
SNJ54AS174FK‡
SNJ54ALS175FK
TOP-SIDE
MARKING
SN74ALS174N
SN74AS174N
SN74ALS175N
SN74AS175BN
ALS174
AS174
ALS175
AS175B
ALS174
74AS174
ALS175
74AS175B
SNJ54ALS174J
SNJ54AS174J
SNJ54ALS175J
SNJ54AS175BJ
SNJ54ALS174W
SNJ54ALS175W
SNJ54ALS174FK
SNJ54AS174FK
SNJ54ALS175FK
LCCC – FK
Tube
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
‡ This orderable is not recommended for new designs.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR
L
H
H
H
CLK
X
↑
↑
L
D
X
H
L
X
OUTPUTS
Q
L
H
L
Q0
Q§
H
L
H
Q0
§ ’ALS175 and ’AS175B only
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
logic diagrams (positive logic)
’ALS174, ’AS174
CLR
1
CLK
9
’ALS175,
’AS175B
CLK
1D
9
3
CLR
1D
C1
R
2
1Q
1D
1
4
1D
C1
R
2
1Q
1Q
3
To Five Other Channels
Pin numbers shown are for the D, J, N, NS, and W packages.
To Three Other Channels
absolute maximum ratings over operating free-air temperature range, SN54/74ALS174,
SN54/74ALS175 (unless otherwise noted)
†
Supply voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, V
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance,
θ
JA
(see Note 1): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
SN54ALS174
SN54ALS175
MIN
VCC
VIH
VIL
IOH
IOL
TA
Supply voltage
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
–55
4.5
2
0.8
–0.4
4
125
0
NOM
5
MAX
5.5
SN74ALS174
SN74ALS175
MIN
4.5
2
0.8
–0.4
8
70
NOM
5
MAX
5.5
V
V
V
mA
mA
°C
UNIT
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
II
IIH
IIL
IO‡
ICC
’ALS174
’ALS175
All others
CLK
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
VCC = 4 5 V
4.5
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5 5 V
5.5 V,
VCC = 5.5 V,
VCC = 5 5 V
5.5 V,
II = –18 mA
IOH = –0.4 mA
IOL = 4 mA
IOL = 8 mA
VI = 7 V
VI = 2.7 V
VI = 0 4 V
0.4
VO = 2.25 V
See Note 3
–20
11
8
SN54ALS174
SN54ALS175
MIN
VCC– 2
0.25
0.4
0.1
20
–0.1
–0.15
–112
19
14
–30
11
9
–112
19
14
TYP†
MAX
–1.5
VCC– 2
0.25
0.35
0.4
0.5
0.1
20
–0.1
SN74ALS174
SN74ALS175
MIN
TYP†
MAX
–1.5
V
V
V
mA
µA
mA
mA
mA
UNIT
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.
NOTE 3: ICC is measured with D inputs and CLR grounded, and CLK at 4.5 V.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
SN54ALS174
SN54ALS175
MIN
fclock
tw
Clock frequency
CLR low
Pulse duration
CLK high
CLK low
tsu
th
Data
Set p time before CLK↑
Setup
Hold time, data after CLK↑
CLR inactive
15
12.5
12.5
15
8
0
MAX
40
10
10
10
10
6
0
ns
ns
ns
SN74ALS174
SN74ALS175
MIN
MAX
50
MHz
UNIT
switching characteristics (see Figure 1)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500
Ω
,
TA = MIN to MAX§
SN54ALS174
SN74ALS174
SN54ALS175
SN74ALS175
MIN
fmax
tPLH
tPHL
tPLH
40
CLR
CLK
Any Q
y
(or Q, ’ALS175)
Any Q
y
(or Q, ’ALS175)
3
5
3
20
30
20
MAX
MIN
50
5
8
3
18
23
15
17
MAX
MHz
ns
ns
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
UNIT
tPHL
5
24
5
§ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
absolute maximum ratings over operating free-air temperature range, SN54/74AS174,
SN54/74AS175B (unless otherwise noted)
†
Supply voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, V
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance,
θ
JA
(see Note 1): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
SN54AS174
SN54AS175B
MIN
VCC
VIH
VIL
IOH
IOL
TA
Supply voltage
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
–55
4.5
2
0.8
–2
20
125
0
NOM
5
MAX
5.5
SN74AS174
SN74AS175B
MIN
4.5
2
0.8
–2
20
70
NOM
5
MAX
5.5
V
V
V
mA
mA
°C
UNIT
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
II
IIH
IIL
IO§
ICC
’AS174
’AS175B
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
VCC = 4.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5 5 V
5.5 V,
II = –18 mA
IOH = –2 mA
IOL = 20 mA
VI = 7 V
VI = 2.7 V
VI = 0.4 V
VO = 2.25 V
See Note 4
–30
30
22.5
SN54AS174
SN54AS175B
MIN
VCC– 2
0.35
0.5
0.1
20
–0.5
–112
45
34
–30
30
22.5
TYP‡
MAX
–1.2
VCC– 2
0.35
0.5
0.1
20
–0.5
–112
45
34
SN74AS174
SN74AS175B
MIN
TYP‡
MAX
–1.2
V
V
V
mA
µA
mA
mA
mA
UNIT
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.
NOTE 4: ICC is measured with D inputs, CLR, and CLK grounded.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5
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