16-Bit 500 kSPS PulSAR
®
Unipolar ADC with Reference
AD7666
FEATURES
2.5 V internal reference: typical drift 3 ppm/°C
Guaranteed max drift 15 ppm/°C
Throughput: 500 kSPS
INL: ±2.0 LSB max (±0.0038% of full scale)
16-bit resolution with no missing codes
S/(N+D): 88 dB min @ 20 kHz
THD: –96 dB max @ 20 kHz
Analog input voltage range: 0 V to 2.5 V
Both AC and DC specifications
No pipeline delay
Parallel and serial 5 V/3 V interface
SPI
®
/QSPI
TM
/MICROWIRE
TM
/DSP compatible
Single 5 V supply operation
Power dissipation
66 mW typ, 132 µW @ 1 kSPS without REF
81 mW typ with REF
48-lead LQFP and 48-lead LFCSP packages
Pin-to-pin compatible with PulSAR ADCs
AGND
AVDD
REF
FUNCTIONAL BLOCK DIAGRAM
REFBUFIN REF REFGND
DVDD
DGND
OVDD
SERIAL
PORT
SWITCHED
CAP DAC
PARALLEL
INTERFACE
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
16
DATA[15:0]
BUSY
RD
CS
SER/PAR
03034-0-001
AD7666
OGND
IN
INGND
PDREF
PDBUF
PD
RESET
OB/2C
BYTESWAP
CNVST
Figure 1. Functional Block Diagram
Table 1. PulSAR Selection
Type/kSPS
Pseudo-
Differential
True Bipolar
True
Differential
18-Bit
Multichannel/
Simultaneous
100–250
AD7651
AD7660/AD7661
AD7663
AD7675
AD7678
500–570
AD7650/AD7652
AD7664/AD7666
AD7665
AD7676
AD7679
AD7654
AD7655
800–
1000
AD7653
AD7667
AD7671
AD7677
AD7674
APPLICATIONS
Data acquisition
Medical instruments
Digital signal processing
Spectrum analysis
Instrumentation
Battery-powered systems
Process control
PRODUCT HIGHLIGHTS
1.
Fast Throughput.
The AD7666 is a 500 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
Superior INL.
The AD7666 has a maximum integral nonlinearity of
2.0 LSB with no missing 16-bit codes.
Internal Reference.
The AD7666 has an internal reference with a typical
temperature drift of 3 ppm/°C.
Single-Supply Operation.
The AD7666 operates from a single 5 V supply. Its power
dissipation decreases with throughput.
Serial or Parallel Interface.
Versatile parallel or 2-wire serial interface arrangement is
compatible with both 3 V and 5 V logic.
GENERAL DESCRIPTION
The AD7666* is a 16-bit, 500 kSPS, charge redistribution SAR
analog-to-digital converter that operates from a single 5 V
power supply. The part contains a high speed, 16-bit sampling
ADC, an internal conversion clock, internal reference, error
correction circuits, and both serial and parallel system inter-
face ports. The AD7666 is hardware factory-calibrated and
comprehensively tested to ensure ac parameters such as signal-
to-noise ratio (SNR) and total harmonic distortion (THD), in
addition to the more traditional dc parameters of gain, offset,
and linearity.
The AD7666 is available in a 48-lead LQFP and a tiny 48-lead
LFCSP, with operation specified from –40°C to +85°C.
*
2.
3.
4.
5.
Patent Pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD7666
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Definitions of Specifications ......................................................... 11
Typical Performance Characteristics ........................................... 12
Circuit Information ........................................................................ 16
Converter Operation.................................................................. 16
Typical Connection Diagram ................................................... 18
Power Dissipation versus Throughput .................................... 20
Conversion Control.................................................................... 21
Digital Interface.......................................................................... 22
Parallel Interface......................................................................... 22
Serial Interface ............................................................................ 22
Master Serial Interface............................................................... 23
Slave Serial Interface .................................................................. 24
Microprocessor Interfacing....................................................... 26
Application Hints ........................................................................... 27
Bipolar and Wider Input Ranges .............................................. 27
Layout .......................................................................................... 27
Evaluating the AD7666’s Performance .................................... 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD7666
SPECIFICATIONS
Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Operating Input Voltage
Analog Input CMRR
Input Current
Input Impedance
1
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
DC ACCURACY
Integral Linearity Error
No Missing Codes
Differential Linearity Error
Transition Noise
Unipolar Zero Error, T
MIN
to T
MAX3
Unipolar Zero Error Temperature Drift
Full-Scale Error, T
MIN
to T
MAX 3
Full-Scale Error Temperature Drift
Power Supply Sensitivity
AC ACCURACY
Signal-to-Noise
Spurious Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
–3 dB Input Bandwidth
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
REFERENCE
Internal Reference Voltage
Internal Reference Temperature Drift
Output Voltage Hysteresis
Long Term Drift
Line Regulation
Turn-On Settling Time
Temperature Pin
Voltage Output @ 25°C
Temperature Sensitivity
Output Resistance
External Reference Voltage Range
External Reference Current Drain
Full-Scale Step
V
REF
@ 25°C
–40°C to +85°C
–40°C to +85°C
AVDD = 5 V ± 5%
C
REF
= 10 µF
2.493
2.5
±3
50
100
±15
5
300
1
4
2.5
120
Conditions
Min
16
0
–0.1
–0.1
65
7.7
Typ
Max
Unit
Bits
V
V
V
dB
µA
V
IN
– V
INGND
V
IN
V
INGND
f
IN
= 10 kHz
500 kSPS Throughput
V
REF
+3
+0.5
0
–2.0
16
–1.0
0.7
2
500
+2.0
+1.5
±5
±0.5
µs
kSPS
LSB
2
Bits
LSB
LSB
LSB
ppm/°C
% of FSR
ppm/°C
LSB
dB
4
dB
dB
dB
dB
MHz
ns
ps rms
REF = 2.5 V
AVDD = 5 V ± 5%
f
IN
= 20 kHz
f
IN
= 20 kHz
f
IN
= 20 kHz
f
IN
= 20 kHz
–60 dB Input, f
IN
= 20 kHz
88
96
88
±1.4
±2
89.2
107
–106
89.1
30
12
2
5
±0.08
–96
750
2.507
±15
ns
V
ppm/°C
ppm
ppm/1000 Hours
ppm/V
ms
mV
mV/°C
kΩ
V
µA
2.3
500 kSPS Throughput
AVDD – 1.85
Rev. 0 | Page 3 of 28
AD7666
Parameter
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
DIGITAL OUTPUTS
Data Format
5
Pipeline Delay
6
V
OL
V
OH
POWER SUPPLIES
Specified Performance
AVDD
DVDD
OVDD
Operating Current
AVDD
8
AVDD
9
DVDD
10
OVDD
10
Power Dissipation without REF
8, 10
Power Dissipation with REF
8, 10
TEMPERATURE RANGE
11
Specified Performance
Conditions
Min
Typ
Max
Unit
–0.3
2.0
–1
–1
+0.8
DVDD + 0.3
+1
+1
V
V
µA
µA
I
SINK
= 1.6 mA
I
SOURCE
= –500 µA
0.4
OVDD – 0.6
V
V
4.75
4.75
2.7
500 kSPS Throughput
With Reference and Buffer
Reference and Buffer Alone
5
5
5.25
5.25
5.25
7
V
V
V
mA
mA
mA
µA
mW
µW
mW
°C
500 kSPS Throughput
1 kSPS Throughput
500 kSPS Throughput
T
MIN
to T
MAX
–40
12.2
3
4.1
102
66
132
81
75
90
+85
1
2
See Analog Input section.
LSB means least significant bit. With the 0 V to 2.5 V input range, 1 LSB is 38.15 µV.
3
See the Definitions of Specifications section. These specifications do not include the error contribution from the external reference.
4
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
5
Parallel or Serial 16-Bit.
6
Conversion results are available immediately after completed conversion.
7
The max should be the minimum of 5.25 V and DVDD + 0.3 V.
8
With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH.
9
With PDREF, PDBUF LOW and PD HIGH.
10
Tested in parallel reading mode.
11
Consult factory for extended temperature range.
Rev. 0 | Page 4 of 28
AD7666
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted
Parameter
Refer to Figure 33 and Figure 34
Convert Pulse Width
Time between Conversions
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except Master Serial Read after Convert
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulse Width
Refer to Figure 35, Figure 36, and Figure 37 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
Refer to Figure 39 and Figure 40 (Master Serial Interface Modes)
1
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
1
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period
2
Internal SCLK HIGH
2
Internal SCLK LOW
2
SDOUT Valid Setup Time
2
SDOUT Valid Hold Time
2
SCLK Last Edge to SYNC Delay
2
CS HIGH to SYNC HI-Z
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert
2
CNVST LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay
Refer to Figure 41 and Figure 42 (Slave Serial Interface Modes)
1
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
Symbol
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
t
30
t
31
t
32
t
33
t
34
t
35
t
36
t
37
Min
10
2
35
1.25
2
10
1.25
750
10
1.25
12
5
45
15
10
10
10
525
3
25
12
7
4
2
3
40
Typ
Max
Unit
ns
µs
ns
µs
ns
ns
µs
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
10
10
10
See Table 4
1.25
25
5
3
5
5
25
10
10
18
1
2
In serial interface mode, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
In serial master read during convert mode. See Table 4 for serial master read after convert mode.
Rev. 0 | Page 5 of 28
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