IBM0418A4CFLBB-3 datasheet, PDF

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IBM0418A4CFLBB-3: DescriptionStandard SRAM, 256KX18, 1.8ns, CMOS, PBGA153, BGA-153; Categorystorage storage; File Size147KB，26 Pages; ManufacturerIBM; Websitehttp://www.ibm.com

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IBM0418A4CFLBB-3 Overview

Standard SRAM, 256KX18, 1.8ns, CMOS, PBGA153, BGA-153

IBM0418A4CFLBB-3 Parametric

Parameter Name	Attribute value
Maker	IBM
Parts packaging code	BGA
package instruction	BGA,
Contacts	153
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	1.8 ns
JESD-30 code	R-PBGA-B153
length	22 mm
memory density	4718592 bit
Memory IC Type	STANDARD SRAM
memory width	18
Number of functions	1
Number of terminals	153
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	256KX18
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	2.679 mm
Maximum supply voltage (Vsup)	2.75 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	14 mm

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IBM0418A8CFLBB

IBM0418A4CFLBB

Preliminary

IBM0436A8CFLBB

IBM0436A4CFLBB

8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM

Features

• 8Mb: 256K x 36 or 512K x 18 organizations

4Mb: 128K x 36 or 256K x 18 organizations

• CMOS Technology

• Double Data Rate and Single Data Rate Syn-

chronous Modes of Operation

• Pipeline Mode of Operation

• Self-Timed Late Write with Full Data Coherency

• Single Differential Extended HSTL Clock

• +2.5V Power Supply, Ground, 1.6V V

DDQ

, and

1.05V V

REF

• Extended HSTL Input

• HSTL Outputs

• Registered Addresses, Controls, and Data Ins

• Burst Mode of operation

• Common I/O

• Asynchronous Output Enable

• Boundary Scan using limited set of JTAG

1149.1 functions

• 9 x 17 Bump Ball Grid Array Package with

SRAM JEDEC Standard Pinout and Boundary

SCAN Order

• Programmable Impedance Output Drivers

Description

The IBM0436A4CFLBB, IBM0418A4CFLBB,

IBM0418A8CFLBB, and IBM0436A8CFLBB

SRAM

are Synchronous Pipeline Mode, high-per-

formance CMOS Static Random Access Memories

that are versatile, have wide I/O, and achieve 3.0ns

cycle times. Differential CK clocks are used to ini-

tiate the read/write operation and all internal opera-

tions are self-timed. At the rising edge of the CK

clock, all Addresses, Controls, and Data Ins are reg-

istered internally. Data Outs are updated from out-

put registers off the next rising and falling edge of

the K clock, hence the Double Data Rate. Internal

Write buffers allow write data to follow one cycle

after addresses and controls. The chip is operated

with a single +2.5V power supply and is compatible

with HSTL I/O interfaces.

cddrh251620.07

12/00

Use is further subject to the provisions at the end of this document.

Page 1 of 26

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