E2L0054-28-Z2
¡ Semiconductor
¡ Semiconductor
MSM51V8221A
262,214-Word
¥
8-Bit Field Memory
This version: Dec. 1998
MSM51V8221A
Previous version: Mar. 1998
DESCRIPTION
The OKI MSM51V8221A is a high performance 2-Mbit, 256K
¥
8-bit, Field Memory. It is designed
for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital
movies and Multi-media systems. It is a FRAM for wide or low end use as general commodity
TVs and VTRs, exclusively. The MSM51V8221A is not designed for the other use or high end
use in medical systems, professional graphics systems which require long term picture, and
data storage systems and others. The 2-Mbit capacity fits one field of a conventional NTSC TV
screen.
Each of the 8-bit planes has separate serial write and read ports. These employ independent control
clocks to support asynchronous read and write operations. Different clock rates are also supported,
which allow alternate data rates between write and read data streams.
The MSM51V8221A provides high speed FIFO, First-In First-Out, operation without external
refreshing: it refreshes its DRAM storage cells automatically, so that it appears fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial
access operation, so that serial read and/or write control clock can be halted high or low for any
duration as long as the power is on. Internal conflicts of memory access and refreshing operations
are prevented by special arbitration logic.
The MSM51V8221A's function is simple, and similar to a digital delay device whose delay-bit-length
is easily set by reset timing. The delay length, and the number of read delay clocks between write
and read, is determined by externally controlled write and read reset timings.
Additional SRAM serial registers, or line buffers for the initial access of 256
¥
8-bit enable high speed
first-bit-access with no clock delay just after the write or read reset timings.
The MSM51V8221A is similar in operation and functionality to OKI 1-Mbit Field Memory
MSM51V4221C. It has a write mask function or input enable function (IE), and read-data skipping
function or output enable function (OE). The differences between write enable (WE) and input
enable (IE), and between read enable (RE) and output enable (OE) are that WE and RE can stop serial
write/read address increments, but IE and OE cannot stop the increment, when write/read clocking
is continuously applied to MSM51V8221A. The input enable (IE) function allows the user to write
into selected locations of the memory only, leaving the rest of the memory contents unchanged. This
facilitates data processing to display a "picture in picture" on a TV screen.
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¡ Semiconductor
MSM51V8221A
FEATURES
• Single power supply : 3.3 V
±0.3
V
• 512 Rows
¥
512 Columns
¥
8 bits
• Fast FIFO (First-In First-Out) operation
• High speed asynchronous serial access
Read/write cycle time
30 ns/40 ns
Access time
30 ns/35 ns
• Functional compatibility with OKI MSM51V4221C
• Write mask function (Input enable control)
• Data skipping function (Output enable control)
• Self refresh (No refresh control is required)
• Package options :
28-pin 400 mil plastic ZIP
(ZIP28-P-400-1.27)
28-pin 400 mil plastic SOJ
(SOJ28-P-400-1.27)
28-pin 430 mil plastic SOP
(SOP28-P-430-1.27-K)
(Product : MSM51V8221A-xxZS)
(Product : MSM51V8221A-xxJS)
(Product : MSM51V8221A-xxGS-K)
xx indicates speed rank.
PRODUCT FAMILY
Family
MSM51V8221A-30ZS
MSM51V8221A-40ZS
MSM51V8221A-30JS
MSM51V8221A-40JS
MSM51V8221A-30GS-K
MSM51V8221A-40GS-K
Access Time (Max.)
30 ns
35 ns
30 ns
35 ns
30 ns
35 ns
Cycle Time (Min.)
30 ns
40 ns
30 ns
40 ns
30 ns
40 ns
Package
400 mil 28-pin ZIP
400 mil 28-pin SOJ
430 mil 28-pin SOP
2/16
¡ Semiconductor
PIN CONFIGURATION (TOP VIEW)
WE
D
IN
0
D
IN
2
V
CC
D
IN
5
1
3
5
7
9
2
4
6
8
IE
D
IN
1
D
IN
3
D
IN
4
10 D
IN
6
12 RSTW
14 NC
16 RE
18 D
OUT
7
20 D
OUT
5
22 V
SS
24 D
OUT
2
26 D
OUT
0
28 SRCK
D
IN
7 11
SWCK 13
NC 15
OE 17
D
OUT
6 19
D
OUT
4 21
D
OUT
3 23
D
OUT
1 25
RSTR 27
D
IN
4 1
D
IN
5 2
D
IN
6 3
D
IN
7 4
28 V
CC
D
IN
4 1
D
IN
5 2
D
IN
6 3
D
IN
7 4
27 D
IN
3
26 D
IN
2
25 D
IN
1
24 D
IN
0
23 IE
22 WE
21 NC
RSTW 5
NC 7
RE 8
OE 9
RSTW 5
SWCK 6
SWCK 6
NC 7
RE 8
OE 9
20 SRCK
19 RSTR
D
OUT
7 10
D
OUT
6 11
D
OUT
5 12
D
OUT
4 13
D
OUT
7 10
D
OUT
6 11
D
OUT
5 12
D
OUT
4 13
V
SS
14
18 D
OUT
0
17 D
OUT
1
16 D
OUT
2
15 D
OUT
3
V
SS
14
28-Pin Plastic SOJ
MSM51V8221A
28 V
CC
27 D
IN
3
26 D
IN
2
25 D
IN
1
24 D
IN
0
23 IE
22 WE
21 NC
20 SRCK
19 RSTR
18 D
OUT
0
17 D
OUT
1
16 D
OUT
2
15 D
OUT
3
28-Pin Plastic SOP
28-Pin Plastic ZIP
Pin Name
SWCK
SRCK
WE
RE
IE
OE
RSTW
RSTR
D
IN
0 - 7
D
OUT
0 - 7
V
CC
V
SS
NC
Function
Serial Write Clock
Serial Read Clock
Write Enable
Read Enable
Input Enable
Output Enable
Write Reset Clock
Read Reset Clock
Data Input
Data Output
Power Supply (3.3 V)
Ground (0 V)
No Connection
3/16
¡ Semiconductor
D
OUT
(¥ 8)
OE
RE
BLOCK DIAGRAM
RSTR
SRCK
Data-out
Buffer (¥ 8)
Serial
Read
Controller
512-Word Serial Read Register (¥ 8)
Read Line Buffer
Low-Half (¥ 8)
256 (¥ 8)
71-Word
Sub-Register (¥ 8)
256K (¥ 8)
Memory
Array
71-Word
Sub-Register (¥ 8)
256 (¥ 8)
Write Line Buffer
Low-Half (¥ 8)
256 (¥ 8)
Write Line Buffer
High-Half (¥ 8)
Clock
Oscillator
X
Decoder
Read/Write
and Refresh
Controller
Read Line Buffer
High-Half (¥ 8)
256 (¥ 8)
512-Word Serial Write Register (¥ 8)
V
BB
Generator
Data-in
Buffer (¥ 8)
Serial
Write
Controller
MSM51V8221A
4/16
D
IN
(¥ 8)
IE
WE
RSTW
SWCK
¡ Semiconductor
MSM51V8221A
OPERATION
Write Operation
The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is
accomplished by cycling SWCK, and holding WE high after the write address pointer reset operation
or RSTW.
Each write operation, which begins after RSTW, must contain at least 80 active write cycles, i.e.
SWCK cycles while WE is high. To transfer the last data to the DRAM array, which at that time
is stored in the serial data registers attached to the DRAM array, an RSTW operation is required
after the last SWCK cycle.
Write Reset : RSTW
The first positive transition of SWCK after RSTW becomes high resets the write address counters to
zero. RSTW setup and hold times are referenced to the rising edge of SWCK. Because the write reset
function is solely controlled by the SWCK rising edge after the high level of RSTW, the states of WE
and IE are ignored in the write reset cycle.
Before RSTW may be brought high again for a further reset operation, it must be low for at least two
SWCK cycles.
Data Inputs : D
IN
0 - 7
Write Clock : SWCK
The SWCK latches the input data on chip when WE is high, and also increments the internal write
address pointer. Data-in setup time t
DS
, and hold time t
DH
are referenced to the rising edge of SWCK.
Write Enable : WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low level
disables the input and holds the internal write address pointer. There are no WE disable time (low)
and WE enable time (high) restrictions, because the MSM51V8221A is in fully static operation as long
as the power is on. Note that WE setup and hold times are referenced to the rising edge of SWCK.
Input Enable : IE
IE is used to enable/disable writing into memory. IE high level enables writing. The internal write
address pointer is always incremented by cycling SWCK regardless of the IE level. Note that IE setup
and hold times are referenced to the rising edge of SWCK.
5/16
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