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X9251TV24

Description
Quad Digitally-Controlled (XDCP) Potentiometer
Categoryaccessories   
File Size833KB,21 Pages
ManufacturerIntersil ( Renesas )
Websitehttp://www.intersil.com/cda/home/
Download Datasheet View All

X9251TV24 Overview

Quad Digitally-Controlled (XDCP) Potentiometer

DATASHEET
X9251
Single Supply/Low Power/256-Tap/SPI Bus, Quad Digitally-Controlled (XDCP™)
Potentiometer
The X9251 integrates four digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
SPI bus interface. Each potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and four nonvolatile
Data Registers that can be directly written to and read by the
user. The content of the WCR controls the position of the wiper.
At power-up, the device recalls the content of the default Data
Registers of each DCP (DR00, DR10, DR20, and DR30) to the
corresponding WCR.
The XDCP can be used as a three terminal potentiometer or as
a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
FN8166
Rev 6.00
December 3, 2014
Features
• Four potentiometers in one package
• 256 resistor taps–0.4% resolution
• SPI serial interface for write, read, and transfer operations of
the potentiometer
• Wiper resistance: 100Ω typical at V
CC
= 5V
• 4 Nonvolatile data registers for each potentiometer
• Nonvolatile storage of multiple wiper positions
• Standby current <5µA max
• V
CC
: 2.7V to 5.5V operation
• 50kΩ version of total resistance
• 100 year data retention
• Single supply version of X9250
• Endurance: 100,000 data changes per bit per register
• 24 Ld SOIC, 24 Ld TSSOP
• Low power CMOS
• Pb-free (RoHS compliant)
V
CC
R
H0
R
H1
R
H2
R
H3
HOLD
A1
A0
SO
SI
SCK
CS
SPI
Interface
WCR0
DR00
DR01
DR02
DR03
DCP0
POWER UP,
INTERFACE
CONTROL
AND
STATUS
WCR1
DR10
DR11
DR12
DR13
DCP1
WCR2
DR20
DR21
DR22
DR23
DCP2
WCR3
DR30
DR31
DR32
DR33
DCP3
V
SS
WP
R
W0
R
L0
R
W1
R
L1
R
W2
R
L2
R
W3
R
L3
FIGURE 1. FUNCTIONAL DIAGRAM
FN8166 Rev 6.00
December 3, 2014
Page 1 of 21
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