MA9264
MA9264
Radiation Hard 8192x8 Bit Static RAM
Replaces June 1999 version, DS3692-6.0
DS3692-7.0 January 2000
The MA9264 64k Static RAM is configured as 8192x8 bits and
manufactured using CMOS-SOS high performance, radiation hard,
1.5µm technology.
The design uses a 6 transistor cell and has full static operation with
no clock or timing strobe required. Address input buffers are deselected
when chip select is in the HIGH state.
See Application Note “Overview of the Dynex Semiconductor
Radiation Hard 1.5µm CMOS/SOS SRAM Range”.
Operation Mode
Read
Write
Output Disable
Standby
CS
L
L
L
H
X
CE
H
H
H
X
L
OE WE
L
X
H
X
X
H
L
H
X
X
I/O
D OUT
D IN
High Z
High Z
X
ISB2
ISB1
Power
FEATURES
s
1.5µm CMOS-SOS Technology
s
Latch-up Free
s
Fast Access Time 70ns Typical
s
Total Dose 10
6
Rad(Si)
s
Transient Upset >10
11
Rad(Si)/sec
s
SEU 4.3 x 10
-11
Errors/bitday
s
Single 5V Supply
s
Three State Output
s
Low Standby Current 100µA Typical
s
-55°C to +125°C Operation
s
All Inputs and Outputs Fully TTL or CMOS
Compatible
s
Fully Static Operation
Figure 1: Truth Table
A12
A9
A8
A4
A3
A6
A5
A7
A
D
D
R
E
S
S
B
U
F
F
E
R
R
O
W
D
E
C
O
D
E
R
CS
CE
WE
OE
A10
A0
A1
A2
A11
Figure 2: Block Diagram
1/15
MA9264
SIGNAL DEFINITIONS
A0-12
Address input pins which select a particular eight bit word within
the memory array.
D0-7
Bidirectional data pins which serve as data outputs during a read
operation and as data inputs during a write operation.
CS
Chip Select, which, at low level, activates a read or write
operation. When at a high level it defaults the SRAM to a
prechargencondition and holds the data output drivers in a high
impedance state.
WE
Write Enable which when at a low level enables a write and holds
data output drivers in a high impedance state. When at a high
level, it enables a read.
OE
Output Enable which when at a high level holds the data output
drivers in a high impedance state. When at a low level, data
output driver state is defined by
CS, WE
and CE. If this signal is
not used it must be connected to VSS.
CE
Chip Enable which when at a high level allows normal operation.
When at a low level it defaults the SRAM to a precharge
condition, disables the input circuits on all input pins and holds
the data output drivers in a high impedance state. If this signal
is not used it must be connected to VDD.
2/15
MA9264
CHARACTERISTICS AND RATINGS
Symbol
V
CC
V
I
T
A
T
S
Parameter
Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
Min.
-0.5
-0.3
-55
-65
Max.
7.0
V
DD
+0.3
125
150
Units
V
V
°C
°C
Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and
functlonal operation of the device at these condltions,
or at any other condition above those indicated in the
operations section of this specification, is not Implied
Exposure to absolute maxlmum rating conditions for
extended perlods may affect device reliability.
Figure 3: Absolute Maximum Ratings
Notes for Tables 4 and 5:
Characteristics apply to pre radiation at T
A
= -55°C to +125°C with V
DD
= 5V
±10%
and to post 100k Rad(Si) total dose
radiation at T
A
= 25°C with V
DD
= 5V
±10%
(characteristics at higher radiation levels available on request). GROUP A
SUBGROUPS 1, 2, 3.
Symbol
V
DD
V
lH
V
lL
V
OH1
V
OH2
V
OL
I
LI
I
LO
I
SB1
Parameter
Supply voltage
Logical ‘1’ Input Voltage
Logical ‘0’ Input Voltage
Logical ‘1’ Output Voltage
Logical ‘1’ Output Voltage
Logical ‘0’ Output Voltage
Input Leakage Current
Output Leakage Current
Selected Static Current (CMOS)
Conditions
-
-
-
I
OH1
= -2mA
I
OH2
= -1mA
I
OL
= 4mA
V
IN
= V
DD
or V
SS
All inputs
Chip disabled, V
OUT
= V
DD
or V
SS
All inputs = V
DD
-0.2V
except
CS
= V
SS
+0.2V
f
RC
= 1MHz, all inputs
switching, V
IH
= V
DD
-0.2V
CS
= V
DD
-0.2V
CE = V
SS
+0.2V
(TTL)
(CMOS)
(TTL)
(CMOS)
(Option)
Min.
4.5
V
DD
/2
0.8 V
DD
V
SS
V
SS
2.4
V
DD
-0.5
-
-
-
-
Typ.
5.0
-
-
-
-
-
-
-
-
-
0.1
Max.
5.5
V
DD
V
DD
0.8
0.2 V
DD
-
-
0.4
±10
±10
10
Units
V
V
V
V
V
V
V
V
µA
µA
mA
I
DD
Dynamic Operating Current
(CMOS)
Standby Supply Current
-
6
18
mA
I
SB2
-
0.1
10
mA
Figure 4: Electrical Characteristics
Symbol
V
DR
I
DDR
Parameter
V
CC
for Data Retention
Data Retention Current
Conditions
CS
= V
DR,
CE = V
SS
CS
= V
DR
, V
DR
= 2.0V
CE = V
SS
(Option)
Min.
2.0
-
Typ.
-
0.05
Max.
-
4
Units
V
mA
Figure 5: Data Retention Characteristics
3/15
MA9264
AC CHARACTERISTICS
Conditions of Test for Tables 5 and 6:
1. Input pulse = V
SS
to 3.0V (TTL) and V
SS
to 4.0V (CMOS).
2. Times measurement reference level = 1.5V.
3. Input Rise and Fall times
≤5ns.
4. Output load 1TTL gate and CL = 60pF.
5. Transition is measured at
±500mV
from steady state.
6. This parameter is sampled and not 100% tested.
Notes for Tables 6 and 7:
Characteristics apply to pre-radiation at T
A
= -55°C to +125°C with V
DD
= 5V±10% and to post 100k Rad(Si) total dose radiation
at T
A
= 25°C with V
DD
= 5V
±10%.
GROUP A SUBGROUPS 9, 10, 11.
Symbol
T
AVAVR
T
AVQV
T
EHQV
T
SLQV
T
EHQX
(5,6)
T
SLQX
(5,6)
T
ELQZ
(5,6)
T
SHQZ
(5,6)
T
AXQX
T
GLQV
T
GLQX
(5,6)
T
GHQZ
(5,6)
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Enable Access Time
Chip Selection to Output in Low Z
Chip Enable to Output in Low Z
Chip Deselection to Output in High Z
Chip Disable to Output in High Z
Output Hold from Address Change
Output Enable Access Time
Output Enable to Output in Low Z
Output Enable to Output in High Z
MAX9264X70
Min Max
70
-
-
-
15
15
0
0
30
-
15
0
-
65
70
70
-
-
20
20
-
25
-
20
MAX9264X95
Min Max
95
-
-
-
15
15
0
0
40
-
15
0
-
90
95
95
-
-
20
20
-
30
-
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 6: Read Cycle AC Electrical Characteristics
Symbol
T
AVAVW
T
EHWH
T
SLWH
T
AVWH
T
AVWL
T
WLWH
T
WHAV
T
WLQZ
(5,6)
T
DVWH
T
WHDX
T
WHQX
(5,6)
Parameter
Write Cycle Tlme
Chip Selection to End of Write
Chip Enable to End of Write
Address Valid to End of Write
Address Set Up Time
Write Pulse Width
Write Recovery Time
Wnte to Output in High Z
Data to Write Time Overlap
Data Hold from Write
Output Active from End to Write
MAX9264X70
Min Max
55
50
50
50
0
40
0
0
25
0
0
-
-
-
-
-
-
-
20
-
-
20
MAX9264X95
Min Max
60
60
60
55
0
45
0
0
30
0
0
-
-
-
-
-
-
-
20
-
-
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 7: Write Cycle AC Electrical Characteristics
4/15
MA9264
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
l
= 0V
V
I/O
= 0V
Min.
-
-
Typ.
3
5
Max.
5
7
Units
pF
pF
Note: T
A
= 25°C and f = 1MHz. Data obtained by characterisation or analysis; not routinely measured.
Figure 8: Capacitance
Symbol
F
T
Parameter
Basic Functionality
Conditions
V
DD
= 4.5V - 5.5V, FREQ = 1MHz
V
IL
= V
SS
, V
IH
= V
DD
, V
OL
≤
1.5V, V
OH
≥
1.5V
TEMP = -55°C to +125°C, GPS PATTERN SET
GROUP A SUBGROUPS 7, 8A, 8B
Figure 9: Functionality
Subgroup
1
2
3
7
8A
8B
9
10
11
Definition
Static characteristics specified in Tables 4 and 5 at +25°C
Static characteristics specified in Tables 4 and 5 at +125°C
Static characteristics specified in Tables 4 and 5 at -55°C
Functional characteristics specified in Table 9 at +25°C
Functional characteristics specified in Table 9 at +125°C
Functional characteristics specified in Table 9 at -55°C
Switching characteristics specified in Tables 6 and 7 at +25°C
Switching characteristics specified in Tables 6 and 7 at +125°C
Switching characteristics specified in Tables 6 and 7 at -55°C
Figure 10: Definition of Subgroups
5/15
京公网安备 11010802033920号
EEWORLD
