®
X55060
64K
Data Sheet
March 28, 2005
FN8133.0
PRELIMINARY
Dual Voltage Monitor with Integrated
System Battery Switch and EEPROM
FEATURES
• Dual voltage monitoring
• Active high and active low reset outputs
• Four standard reset threshold voltages
(4.6/2.9, 4.6/2.6, 2.9/1.6, 2.6/1.6)
—User programmable thresholds
• Lowline Output — Zero delayed POR
• Reset signal valid to V
CC
= 1V
• System battery switch-over circuitry
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<30µA max standby current, watchdog off
• Selectable watchdog timer
—(0.15s, 0.4s, 0.8s, off)
• 64Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect none(0), or all of EEPROM array with
programmable Block Lock
™
protection
BLOCK DIAGRAM
•
•
•
•
—In circuit programmable ROM mode
Minimize EEPROM programming time
—64 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
10MHz SPI interface modes (0,0 & 1,1)
2.7V to 5.5V power supply operation
Available packages — 20-lead TSSOP
DESCRIPTION
This device combines power-on reset control, battery
switch circuit, watchdog timer, supply voltage supervi-
sion, secondary voltage supervision, block lock protect
and serial EEPROM in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
V
OUT
V2MON
V2 Monitor
Logic
+
V2FAIL
V
TRIP2
-
Watchdog Transition
Detector
WP
SO
SI
Data
Register
Command
Decode, Test
& Control
Logic
Protect Logic
Status
Register
EEPROM Array
Watchdog
Timer Reset
WDO
RESET
X-Decoder
Reset &
Watchdog
Timebase
BATT-ON
SCK
CS
512 X 128
V
OUT
V
BATT
V
CC
(V1MON)
System
Battery
Switch
+
RESET/MR
V
OUT
V
CC
Monitor
Logic
V
TRIP1
-
Power-on,
Low Voltage
Reset
Generation
LOWLINE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X55060
A system battery switch circuit compares V
CC
(V1MON)
with V
BATT
input and connects V
OUT
to whichever is
higher. This provides voltage to external SRAM or other
circuits in the event of main power failure. The X55060
can drive 50mA from V
CC
and 250µA from V
BATT
. The
device switches to V
BATT
when V
CC
drops below the
low V
CC
voltage threshold and V
BATT
> V
CC
.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The device’s low V
CC
detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when V
CC
(V1MON) falls below the minimum
V
CC
trip point (V
TRIP1
). RESET/RESET is asserted until
V
CC
returns to proper operating level and stabilizes. A
second voltage monitor circuit tracks the unregulated
PIN CONFIGURATION
20-Pin TSSOP
CS/WDI
NC
SO
RESET
LOWLINE
V2FAIL
V2MON
WP
NC
VSS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
(V1MON)
WDO
RESET/MR
BATT-ON
V
OUT
V
BATT
SCK
NC
NC
SI
supply or monitors a second power supply voltage to
provide a power fail warning. Intersil’s unique circuits
allow the threshold for either voltage monitor to be
reprogrammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.
ORDERING INFORMATION
X55060
Suffix
V20-4.5A
V20I-4.5A
V20-4.5
V20I-4.5
V20-2.7A
V20I-2.7A
V20-2.7
V20I-2.7
Vtrip1
4.6
4.6
2.9
2.6
Vtrip2
2.6
2.9
1.65
1.65
Temp Range
0°C to 70°C
-40°C to 85°C
0°C to 70°C
-40°C to 85°C
0°C to 70°C
-40°C to 85°C
0°C to 70°C
-40°C to 85°C
2
FN8133.0
March 28, 2005
X55060
PIN DESCRIPTION
Pin
1
Name
CS/WDI
Function
Chip Select Input.
CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any opera-
tion after power-up, a HIGH to LOW transition on CS is required.
Watchdog Input.
A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET
going active.
No internal connections
Serial Output.
SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
Reset Output.
RESET is an active HIGH, open drain output which is the inverse of the RESET
output.
Low V
CC
Detect.
This open drain output signal goes LOW when V
CC
< V
TRIP1
and
immediately goes HIGH when V
CC
> V
TRIP1
. This pin goes LOW 250ns before RESET pin.
V2 Voltage Fail Output.
This open drain output goes LOW when V2MON is less than V
TRIP2
and goes HIGH when V2MON exceeds V
TRIP2
. There is no power-up reset delay circuitry on this
pin.
V2 Voltage Monitor Input.
When the V2MON input is less than the V
TRIP2
voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V
SS
or V
CC
when not used.
Write Protect.
The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the Watchdog Timer control and the memory write protect bits.
No internal connections
Ground
Serial Input.
SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on
this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
No internal connections
No internal connections
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output. The rising
edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of
SCK changes the data output on the SO pin.
Battery Supply Voltage.
This input provides a backup supply in the event of a failure of the pri-
mary V
CC
voltage. The V
BATT
voltage typically provides the supply voltage necessary to maintain
the contents of SRAM and also powers the internal logic to “stay awake.” If unused connect
V
BATT
to ground.
2
3
4
5
6
NC
SO
RESET
LOWLINE
V2FAIL
7
V2MON
8
9
10
11
WP
NC
V
SS
SI
12
13
14
NC
NC
SCK
15
V
BATT
3
FN8133.0
March 28, 2005
X55060
PIN DESCRIPTION
(CONTINUED)
Pin
16
Name
V
OUT
Function
Output Voltage.
V
OUT
= V
CC
if V
CC
> V
TRIP1
.
IF V
CC
< V
TRIP1
, then,
V
OUT
= V
CC
if V
CC
> V
BATT
+0.03
V
OUT
= V
BATT
if V
CC
< V
BATT
-0.03
Note:
There is hysteresis around V
BATT
± 0.03V point to avoid oscillation at or near the
switchover voltage. A capacitance of 0.1µF must be connected to Vout to ensure stability.
Battery On.
This open drain output goes HIGH when the V
OUT
switches to V
BATT
and goes LOW
when V
OUT
switches to V
CC
. It is used to drive an external PNP pass transistor when V
CC
= V
OUT
and current requirements are greater than 50mA.
The purpose of this output is to drive an external transistor to get higher operating currents when
the V
CC
supply is fully functional. In the event of a V
CC
failure, the battery voltage is applied to
the V
OUT
pin and the external transistor is turned off. In this “backup condition,” the battery only
needs to supply enough voltage and current to keep SRAM devices from losing their data-there
is no communication at this time.
Output/Manual Reset Input.
This is an Input/Output pin.
RESET Output.
This is an active LOW, open drain output which goes active whenever V
CC
falls
below the minimum V
CC
sense level. When RESET is active communication to the device is inter-
rupted. RESET remains active until V
CC
rises above the minimum V
CC
sense level for 150ms.
RESET also goes active on power-up and remains active for 150ms after the power supply
stabilizes.
MR Input.
This is an active LOW debounced input. When MR is active, the RESET/RESET pins
are asserted. When MR is released, the RESET/RESET remains asserted for t
PURST
, and then re-
leased.
Watchdog Output.
WDO is an active low, open drain output which goes active whenever the
watchdog timer goes active. WDO remains active for 150ms, then returns to the inactive state.
Supply Voltage/V1 Voltage Monitor Input.
When the V1MON input is less than the VTRIP1
voltage, RESET and RESET go ACTIVE.
17
BATT-ON
18
RESET
/MR
19
20
WDO
V
CC
(V1MON)
PRINCIPLES OF OPERATION
Power-On Reset
Application of power to the X55060 activates a Power-
on Reset Circuit. This circuit goes active at about 1V
and pulls the RESET/RESET pin active. This signal
prevents the system microprocessor from starting to
operate with insufficient voltage or prior to stabilization
of the oscillator. When V
CC
exceeds the device V
TRIP1
value for 150ms (nominal) the circuit releases
RESET/RESET, allowing the processor to begin exe-
cuting code.
Low V
CC
(V1MON) Voltage Monitoring
During operation, the X55060 monitors the V
CC
level
and asserts RESET/RESET if supply voltage falls
below a preset minimum V
TRIP1
. During this time the
communication to the device is interrupted. The
RESET/RESET signal also prevents the microproces-
sor from operating in a power fail or brownout condi-
tion. The RESET signal remains active until the
voltage drops below 1V. These also remain active until
V
CC
returns and exceeds V
TRIP1
for t
PURST
.
Low V2MON Voltage Monitoring
The X55060 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum V
TRIP2
. The V2FAIL signal is either ORed with
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. V2FAIL remains active until V2MON
returns and exceeds V
TRIP2
.
The V2MON voltage sensor is powered by V
OUT
. If
V
CC
and V
BATT
go away (i.e. V
OUT
goes away), then
V2MON cannot be monitored.
4
FN8133.0
March 28, 2005
X55060
Figure 1. Two Uses of Dual Voltage Monitoring
X55060
Unregulated
Supply
R1
R2
V2
5V
Reg
V
CC
RESET
V2MON
V2FAIL
V
OUT
X55060
System
Reset
System
Interrupt
Unregulated
Supply
5V
Reg
V
CC
V
OUT
RESET
System
Reset
3.3V
Reg
V2MON
V2FAIL
R1 and R2 selected so V2 = V2MON threshold when
Unregulated supply reaches 6V.
Notice: No external components required to monitor
two voltages.
Watchdog Timer
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the CS/WDI pin. The micro-
processor must toggle the CS/WDI pin HIGH to LOW
periodically prior to the expiration of the watchdog time
out period to prevent the WDO signal going active.
The state of two nonvolatile control bits in the Status
Register determines the watchdog timer period. The
microprocessor can change these watchdog bits by
writing to the status register. The factory default set-
ting disables the watchdog timer.
The Watchdog Timer oscillator stops when in battery
backup mode. It re-starts when V
CC
returns.
System Battery Switch
As long as V
CC
exceeds the low voltage detect thresh-
old V
TRIP1
, V
OUT
is connected to V
CC
through a 5Ω
(typical) switch. When the V
CC
has fallen below V
TRIP
,
then V
CC
is applied to V
OUT
if V
CC
is equal to or
greater than V
BATT
+ 0.03V. When V
CC
drops to less
than V
BATT
- 0.03V, then V
OUT
is connected to V
BATT
through an 80Ω (typical) switch. V
OUT
typically sup-
plies the system static RAM voltage, so the switchover
circuit operates to protect the contents of the static
RAM during a power failure. Typically, when V
CC
has
failed, the SRAMs go into a lower power state and
draw much less current than in their active mode.
When V
CC
returns, V
OUT
switches back to V
CC
when
V
CC
exceeds V
BATT
+ 0.03V. There is a 60mV hyster-
esis around this battery switch threshold to prevent
oscillations between supplies.
While V
CC
is connected to V
OUT
the BATT-ON pin is
pulled LOW. The signal can drive an external PNP
transistor to provide additional current to the external
circuits during normal operation.
Operation
The device is in normal operation with V
CC
as long as
V
CC
> V
TRIP1
. It switches to the battery backup mode
when V
CC
goes away.
Condition
V
CC
> V
TRIP1
V
CC
> V
TRIP1
&
V
BATT
= 0
0
≤
V
CC
V
TRIP1
and V
CC
< V
BATT
Mode of Operation
Normal Operation.
Normal Operation without battery
back up capability.
Battery Backup Mode; RESET
signal is asserted. No communica-
tion to the device is allowed.
5
FN8133.0
March 28, 2005
京公网安备 11010802033920号
EEWORLD
