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IDT709379L7PFG

Description
Dual-Port SRAM, 32KX18, 7.5ns, CMOS, PQFP100, TQFP-100
Categorystorage    storage   
File Size178KB,16 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
Download Datasheet Parametric View All

IDT709379L7PFG Overview

Dual-Port SRAM, 32KX18, 7.5ns, CMOS, PQFP100, TQFP-100

IDT709379L7PFG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instructionLFQFP,
Contacts100
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Maximum access time7.5 ns
JESD-30 codeS-PQFP-G100
JESD-609 codee3
length14 mm
memory density589824 bit
Memory IC TypeDUAL-PORT SRAM
memory width18
Humidity sensitivity level3
Number of functions1
Number of terminals100
word count32768 words
character code32000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX18
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width14 mm
HIGH-SPEED 32/16K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features
IDT709379/69L
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6.5/7.5/9/12ns (max.)
– Insustrial: 9ns (max.)
Low-power operation
– IDT709379/69L
Active: 1.2W (typ.)
Standby: 2.5mW (typ.)
Flow-Through or Pipelined output mode on either Port via
the
FT/PIPE
pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100-pin Thin Quad Flatpack (TQFP) package
Green parts available, see ordering information
Functional Block Diagram
R/
W
L
UB
L
CE
0L
R/
W
R
UB
R
CE
0R
CE
1L
LB
L
OE
L
1
0
0/1
1
0
0/1
CE
1R
LB
R
OE
R
FT
/PIPE
L
0/1
1b 0b
b a
1a 0a
0a 1a
a
0b 1b
b
0/1
FT
/PIPE
R
I/O
9L
-I/O
17L
I/O
0L
-I/O
8L
I/O
Control
I/O
9R
-I/O
17R
I/O
Control
I/O
0R
-I/O
8R
A
14L
(1)
A
0L
CLK
L
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
14R
(1)
A
0R
CLK
R
ADS
L
CNTEN
L
CNTRST
L
ADS
R
CNTEN
R
CNTRST
R
4845 drw 01
NOTE:
1. A
14
X
is a NC for IDT709369.
JULY 2010
1
©2010 Integrated Device Technology, Inc.
DSC-4845/6
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