ISPLSI1016E-80LTN44 datasheet, PDF

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ISPLSI1016E-80LTN44: DescriptionEE PLD, 18.5ns, 64-Cell, CMOS, PQFP44, LEAD FREE, TQFP-44; CategoryProgrammable logic devices Programmable logic; File Size257KB，13 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com; Environmental Compliance

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ISPLSI1016E-80LTN44 Overview

EE PLD, 18.5ns, 64-Cell, CMOS, PQFP44, LEAD FREE, TQFP-44

ISPLSI1016E-80LTN44 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Lattice
Parts packaging code	QFP
package instruction	QFP, QFP44,.47SQ,32
Contacts	44
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	USE ISPLSI1016EA FOR NEW DESIGNS
maximum clock frequency	57 MHz
In-system programmable	YES
JESD-30 code	S-PQFP-G44
JESD-609 code	e3
JTAG BST	NO
length	10 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	32
Number of macro cells	64
Number of terminals	44
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 32 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP44,.47SQ,32
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	240
power supply	5 V
Programmable logic type	EE PLD
propagation delay	18.5 ns
Certification status	Not Qualified
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10 mm

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Lead-

Free

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ispLSI 1016E

In-System Programmable High Density PLD

Functional Block Diagram

Features

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 2000 PLD Gates

— 32 I/O Pins, Four Dedicated Inputs

— 96 Registers

— High-Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

• HIGH-PERFORMANCE E

CMOS

TECHNOLOGY

—

max

= 125 MHz Maximum Operating Frequency

—

= 7.5 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

Output Routing Pool

Array

Global Routing Pool (GRP)

D Q

Logic

D Q

GLB

D Q

CLK

— Reprogram Soldered Device for Faster Prototyping

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

The ispLSI 1016E is a High Density Programmable Logic

Device containing 96 Registers, 32 Universal I/O pins,

four Dedicated Input pins, three Dedicated Clock Input

pins, one Global OE input pin and a Global Routing Pool

(GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 1016E offers

5V non-volatile in-system programmability of the logic, as

well as the interconnect to provide truly reconfigurable

systems. A functional superset of the ispLSI 1016

architecture, the ispLSI 1016E device adds a new global

output enable pin.

The basic unit of logic on the ispLSI 1016E device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1...B7 (see Figure 1). There are a total of 16 GLBs in the

ispLSI 1016E device. Each GLB has 18 inputs, a

programmable AND/OR/Exclusive OR array, and four

outputs which can be configured to be either combinatorial

or registered. Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any other GLB on the device.

— Synchronous and Asynchronous Clocks

— Flexible Pin Placement

— Lead-Free Package Options

to change without notice.

— Optimized Global Routing Pool Provides Global

Interconnectivity

— Programmable Output Slew Rate Control to

Minimize Switching Noise

Description

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

August 2006

1016e_09

Output Routing Pool

0139C1-isp

D Q

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Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Parts packaging code	QFP	QFP	QFP	LCC	LCC	LCC	QFP
package instruction	QFP, QFP44,.47SQ,32	QFP, QFP44,.47SQ,32	QFP, QFP44,.47SQ,32	QCCJ, LDCC44,.7SQ	QCCJ, LDCC44,.7SQ	QCCJ, LDCC44,.7SQ	QFP, QFP44,.47SQ,32
Contacts	44	44	44	44	44	44	44
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Maker	Lattice	-	-	Lattice	Lattice	Lattice	Lattice
Other features	USE ISPLSI1016EA FOR NEW DESIGNS	USE ISPLSI1016EA FOR NEW DESIGNS	USE ISPLSI1016EA FOR NEW DESIGNS	-	-	-	USE ISPLSI1016EA FOR NEW DESIGNS
maximum clock frequency	57 MHz	100 MHz	77 MHz	-	-	-	57 MHz
In-system programmable	YES	YES	YES	-	-	-	YES
JESD-30 code	S-PQFP-G44	S-PQFP-G44	S-PQFP-G44	-	-	-	S-PQFP-G44
JTAG BST	NO	NO	NO	-	-	-	NO
length	10 mm	10 mm	10 mm	-	-	-	10 mm
Humidity sensitivity level	3	3	3	-	-	-	3
Number of I/O lines	32	32	32	-	-	-	32
Number of macro cells	64	64	64	-	-	-	64
Number of terminals	44	44	44	-	-	-	44
Maximum operating temperature	70 °C	70 °C	70 °C	-	-	-	85 °C
organize	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O	0 DEDICATED INPUTS, 32 I/O	-	-	-	0 DEDICATED INPUTS, 32 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	-	-	-	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	-	-	PLASTIC/EPOXY
encapsulated code	QFP	QFP	QFP	-	-	-	QFP
Encapsulate equivalent code	QFP44,.47SQ,32	QFP44,.47SQ,32	QFP44,.47SQ,32	-	-	-	QFP44,.47SQ,32
Package shape	SQUARE	SQUARE	SQUARE	-	-	-	SQUARE
Package form	FLATPACK	FLATPACK	FLATPACK	-	-	-	FLATPACK
Peak Reflow Temperature (Celsius)	240	260	240	-	-	-	NOT SPECIFIED
power supply	5 V	5 V	5 V	-	-	-	5 V
Programmable logic type	EE PLD	EE PLD	EE PLD	-	-	-	EE PLD
propagation delay	18.5 ns	10 ns	13 ns	-	-	-	18.5 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	-	-	-	Not Qualified
Maximum supply voltage	5.25 V	5.25 V	5.25 V	-	-	-	5.5 V
Minimum supply voltage	4.75 V	4.75 V	4.75 V	-	-	-	4.5 V
Nominal supply voltage	5 V	5 V	5 V	-	-	-	5 V
surface mount	YES	YES	YES	-	-	-	YES
technology	CMOS	CMOS	CMOS	-	-	-	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	-	-	-	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING	-	-	-	GULL WING
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	-	-	-	0.8 mm
Terminal location	QUAD	QUAD	QUAD	-	-	-	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	-	-	NOT SPECIFIED
width	10 mm	10 mm	10 mm	-	-	-	10 mm

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