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X40626S14-4.5A

Description
RTC Module With CPU Supervisor
Categoryaccessories   
File Size840KB,22 Pages
ManufacturerIntersil ( Renesas )
Websitehttp://www.intersil.com/cda/home/
Download Datasheet View All

X40626S14-4.5A Overview

RTC Module With CPU Supervisor

DATASHEET
X40626
64K, 8K x 8 Bit Dual Voltage CPU Supervisor with 64K Serial EEPROM
FEATURES
• Dual voltage monitoring
—V
2Mon
operates independent of V
CC
• Watchdog timer with selectable timeout intervals
• Low V
CC
detection and reset assertion
—Four standard reset threshold voltages
—User programmable V
TRIP
threshold
—Reset signal valid to V
CC
=1V
• Low power CMOS
—20µA max standby current, watchdog on
—1µA standby current, watchdog OFF
• 64Kbits of EEPROM
—64 byte page size
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
Block Lock
protection
• 400kHz 2-wire interface
—Slave addressing supports up to 4 devices on
the same bus
FN8119
Rev 0.00
March 28, 2005
• 2.7V to 5.5V power supply operation
• Available Packages
—14-lead SOIC
—14-lead TSSOP
DESCRIPTION
The X40626 combines four popular functions, Power-on
Reset Control, Watchdog Timer, Dual Supply Voltage
Supervision, and Serial EEPROM Memory in one pack-
age. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to stabi-
lize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time-
out interval, the device activates the RESET signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after cycling
the power.
BLOCK DIAGRAM
V2FAIL
V2MON
V2 Monitor
Logic
Watchdog Transition
Detector
WP
SDA
Data
Register
Command
Decode &
Control
Logic
V
CC
Threshold
Reset logic
Block Lock Control
Protect Logic
+
V
TRIP2
-
Watchdog
Timer Reset
RESET
Status
Register
Reset &
Watchdog
Timebase
SCL
S0
S1
64KB
EEPROM
Array
V
CC
V
TRIP
+
-
Power-on and
Low Voltage
Reset
Generation
FN8119 Rev 0.00
March 28, 2005
Page 1 of 22
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