IMPORTANT NOTICE
10 December 2015
1. Global joint venture starts operations as WeEn Semiconductors
Dear customer,
As from November 9th, 2015 NXP Semiconductors N.V. and Beijing JianGuang Asset
Management Co. Ltd established Bipolar Power joint venture (JV),
WeEn Semiconductors,
which
will be used in future Bipolar Power documents together with new contact details.
In this document where the previous NXP references remain, please use the new links as shown
below.
WWW
- For www.nxp.com use
www.ween-semi.com
Email
- For salesaddresses@nxp.com use
salesaddresses@ween-semi.com
For the copyright notice at the bottom of each page (or elsewhere in the document, depending
on the version) “
©
NXP Semiconductors N.V.
{year}.
All rights reserved”
becomes “
©
WeEn
Semiconductors Co., Ltd.
{year}.
All rights reserved”
If you have any questions related to this document, please contact our nearest sales office via e-
mail or phone (details via
salesaddresses@ween-semi.com).
Thank you for your cooperation and understanding,
WeEn Semiconductors
DISCRETE SEMICONDUCTORS
DATA SHEET
BT258X series
Thyristors
logic level
Product
specification
October 2002
NXP
Semiconductors
Product specification
Thyristors
logic level
GENERAL DESCRIPTION
Passivated, sensitive gate thyristors
in a full pack, plastic envelope,
intended for use in general purpose
switching
and
phase
control
applications. These devices are
intended to be interfaced directly to
microcontrollers, logic integrated
circuits and other low power gate
trigger circuits.
BT258X series
QUICK REFERENCE DATA
SYMBOL
V
DRM
,
V
RRM
I
T(AV)
I
T(RMS)
I
TSM
PARAMETER
BT258X-
Repetitive peak off-state
voltages
Average on-state current
RMS on-state current
Non-repetitive peak on-state
current
MAX. MAX. MAX. UNIT
500R
500
5
8
75
600R
600
5
8
75
800R
800
5
8
75
V
A
A
A
PINNING - SOT186A
PIN
1
2
3
DESCRIPTION
cathode
anode
gate
PIN CONFIGURATION
case
SYMBOL
a
k
case isolated
1 2 3
g
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
-
half sine wave; T
hs
≤
90 ˚C
all conduction angles
half sine wave; T
j
= 25 ˚C prior to
surge
t = 10 ms
t = 8.3 ms
t = 10 ms
I
TM
= 10 A; I
G
= 50 mA;
dI
G
/dt = 50 mA/µs
-
-
-
-
-
-
-
-
-
-
-40
-
MAX.
-500R -600R -800R
500
1
600
1
800
5
8
75
82
28
50
2
5
5
0.5
150
125
2
UNIT
V
A
A
A
A
A
2
s
A/µs
A
V
W
W
˚C
˚C
V
DRM
, V
RRM
Repetitive peak off-state
voltages
I
T(AV)
I
T(RMS)
I
TSM
Average on-state current
RMS on-state current
Non-repetitive peak
on-state current
I
2
t
dI
T
/dt
I
GM
V
RGM
P
GM
P
G(AV)
T
stg
T
j
I
2
t for fusing
Repetitive rate of rise of
on-state current after
triggering
Peak gate current
Peak reverse gate voltage
Peak gate power
Average gate power
over any 20 ms period
Storage temperature
Operating junction
temperature
1
Although not recommended, off-state voltages up to 800V may be applied without damage, but the thyristor may
switch to the on-state. The rate of rise of current should not exceed 15 A/µs.
2
Note: Operation above 110˚C may require the use of a gate to cathode resistor of 1kΩ or less.
October 2002
1
Rev 2.000
NXP
Semiconductors
Product specification
Thyristors
logic level
ISOLATION LIMITING VALUE & CHARACTERISTIC
T
hs
= 25 ˚C unless otherwise specified
SYMBOL
V
isol
C
isol
PARAMETER
R.M.S. isolation voltage from all
three terminals to external
heatsink
CONDITIONS
f = 50-60 Hz; sinusoidal
waveform;
R.H.
≤
65% ; clean and dustfree
MIN.
-
BT258X series
TYP.
-
MAX.
2500
UNIT
V
Capacitance from T2 to external f = 1 MHz
heatsink
-
10
-
pF
THERMAL RESISTANCES
SYMBOL
R
th j-hs
R
th j-a
PARAMETER
Thermal resistance
junction to heatsink
Thermal resistance
junction to ambient
CONDITIONS
with heatsink compound
without heatsink compound
in free air
MIN.
-
-
-
TYP.
-
-
55
MAX.
5.0
6.9
-
UNIT
K/W
K/W
K/W
STATIC CHARACTERISTICS
T
j
= 25 ˚C unless otherwise stated
SYMBOL
I
GT
I
L
I
H
V
T
V
GT
I
D
, I
R
PARAMETER
Gate trigger current
Latching current
Holding current
On-state voltage
Gate trigger voltage
Off-state leakage current
CONDITIONS
V
D
= 12 V; I
T
= 0.1 A
V
D
= 12 V; I
GT
= 0.1 A
V
D
= 12 V; I
GT
= 0.1 A
I
T
= 16 A
V
D
= 12 V; I
T
= 0.1 A
V
D
= V
DRM(max)
; I
T
= 0.1 A; T
j
= 110 ˚C
V
D
= V
DRM(max)
; V
R
= V
RRM(max)
; T
j
= 125 ˚C
MIN.
-
-
-
-
-
0.1
-
TYP.
50
0.4
0.3
1.3
0.4
0.2
0.1
MAX.
200
10
6
1.6
1.5
-
0.5
UNIT
µA
mA
mA
V
V
V
mA
DYNAMIC CHARACTERISTICS
T
j
= 25 ˚C unless otherwise stated
SYMBOL
dV
D
/dt
t
gt
t
q
PARAMETER
Critical rate of rise of
off-state voltage
Gate controlled turn-on
time
Circuit commutated
turn-off time
CONDITIONS
V
DM
= 67% V
DRM(max)
; T
j
= 125 ˚C;
exponential waveform; R
GK
= 100
Ω
I
TM
= 10 A; V
D
= V
DRM(max)
; I
G
= 5 mA;
dI
G
/dt = 0.2 A/µs
V
D
= 67% V
DRM(max)
; T
j
= 125 ˚C;
I
TM
= 12 A; V
R
= 24 V; dI
TM
/dt = 10 A/µs;
dV
D
/dt = 2 V/µs; R
GK
= 1 kΩ
MIN.
50
-
-
TYP.
100
2
100
MAX.
-
-
-
UNIT
V/µs
µs
µs
October 2002
2
Rev 2.000
NXP
Semiconductors
Product specification
Thyristors
logic level
BT258X series
Ptot (W)
8
conduction
angle
degrees
30
60
90
120
180
form
factor
(a)
6
4
2.8
2.2
1.9
1.57
1.9
2.2
2.8
4
Ths(max) (˚C)
85
a = 1.57
90
95
100
105
110
80
70
60
50
40
30
20
10
0
ITSM / A
IT
I TSM
time
T
Tj initial = 25 C max
4
2
115
120
0
0
2
4
IT(AV) (A)
6
125
1
10
100
Number of half cycles at 50Hz
1000
Fig.1. Maximum on-state dissipation, P
tot
, versus
average on-state current, I
T(AV)
, where
a = form factor = I
T(RMS)
/ I
T(AV)
.
ITSM / A
Fig.4. Maximum permissible non-repetitive peak
on-state current I
TSM
, versus number of cycles, for
sinusoidal currents, f = 50 Hz.
1000
24
20
16
IT(RMS) / A
dI
T
/dt limit
100
IT
T
I TSM
time
12
8
4
0
0.01
Tj initial = 25 C max
10
10us
100us
T/s
1ms
10ms
0.1
1
surge duration / s
10
Fig.2. Maximum permissible non-repetitive peak
on-state current I
TSM
, versus pulse width t
p
, for
sinusoidal currents, t
p
≤
10ms.
IT(RMS) / A
90 C
Fig.5. Maximum permissible repetitive rms on-state
current I
T(RMS)
, versus surge duration, for sinusoidal
currents, f = 50 Hz; T
hs
≤
90˚C.
VGT(Tj)
VGT(25 C)
9
8
7
6
5
4
3
2
1
1.6
1.4
1.2
1
0.8
0.6
0
-50
0
50
Ths / C
100
150
0.4
-50
0
50
Tj / C
100
150
Fig.3. Maximum permissible rms current I
T(RMS)
,
versus mounting base temperature T
hs
.
Fig.6. Normalised gate trigger voltage
V
GT
(T
j
)/ V
GT
(25˚C), versus junction temperature T
j
.
October 2002
3
Rev 2.000
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