MCM63Z918 datasheet, PDF - EEWORLD Datasheet

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MCM63Z918: Description256K x 36 and 512K x 18 Bit ZBT Fast Static RAM; File Size480KB，36 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MCM63Z918 Overview

256K x 36 and 512K x 18 Bit ZBT Fast Static RAM

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MOTOROLA

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

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by MCM63Z836/D

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256K x 36 and 512K x 18 Bit

ZBT

Fast Static RAM

MCM63Z836

MCM63Z918

Freescale Semiconductor, Inc...

The ZBT RAM is an 8M–bit synchronous fast static RAM designed to provide

Zero Bus Turnaround

. The ZBT RAM allows 100% use of bus cycles during

back–to–back read/write and write/read cycles. The MCM63Z836 (organized as

256K words by 36 bits) and the MCM63Z918 (organized as 512K words by 18

bits) are fabricated in Motorola’s high performance silicon gate CMOS tech-

nology. This device integrates input registers, an output register, a 2–bit address

counter, and high speed SRAM onto a single monolithic circuit for reduced parts

count in communication applications. Synchronous design allows precise cycle

control with the use of an external positive–edge–triggered clock (CK). CMOS

circuitry reduces the overall power consumption of the integrated functions for

greater reliability.

Addresses (SA), data inputs (DQ), and all control signals except output enable

(G) and linear burst order (LBO) are clock (CK) controlled through positive–

edge–triggered noninverting registers.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (CK) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals. Write data is

supplied to the memory one cycle after the write sequence initiation for the flow–

through device, and two cycles after the write sequence initiation for the pipelined

device.

For flow–through read cycles, the SRAM allows output data to simply flow freely from the memory

array. For pipelined read cycles, the SRAM output data is temporarily stored by an edge–triggered

output register and then released to the output buffers at the next rising edge of clock (CK).

The MCM63Z836 and MCM63Z918 operate from a 3.3 V core power supply and all outputs oper-

ate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC Standard JESD8–A and

JESD8–5 compatible.

•

3.3 V

±5%

Core Power Supply, 2.5 V or 3.3 V I/O Supply

•

MCM63Z836 / 918–7 = 7 ns Flow–Through Access / 2.6 ns Pipelined Access (225 MHz)

MCM63Z836 / 918–8 = 8 ns Flow–Through Access / 3 ns Pipelined Access (200 MHz)

MCM63Z836 / 918–8.5 = 8.5 ns Flow–Through Access / 3.5 ns Pipelined Access (166 MHz)

•

Selectable Read/Write Functionality (Flow–Through/Pipelined)

•

Selectable Burst Sequencing Order (Linear/Interleaved)

•

Internally Self–Timed Write Cycle

•

Two–Cycle Deselect (Pipelined)

•

Byte Write Control

•

ADV Controlled Burst

•

Simplified JTAG

•

100–Pin TQFP and 119–Bump PBGA Packages

TQ PACKAGE

TQFP

CASE 983A–01

ZP PACKAGE

PBGA

CASE 999–02

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by

Micron Technology, Inc. and Motorola, Inc.

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 4

12/20/99

Motorola, Inc. 1999

MOTOROLA FAST SRAM

For More Information On This Product,

Go to: www.freescale.com

MCM63Z836•MCM63Z918

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