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FEATURES
44 V Supply Maximum Ratings
15 V Analog Signal Range
Low On Resistance (<24 )
Ultralow Power Dissipation (3.9 W)
Low Leakage (<0.25 nA)
Fast Switching Times
t
ON
<165 ns
t
OFF
<130 ns
Break-Before-Make Switching Action
TTL/CMOS Compatible
Plug-in Replacement for DG411/DG412/DG413
APPLICATIONS
Audio and Video Switching
Automatic Test Equipment
Precision Data Acquisition
Battery Powered Systems
Sample Hold Systems
Communication Systems
LC MOS
Precision Quad SPST Switches
ADG431/ADG432/ADG433
FUNCTIONAL BLOCK DIAGRAMS
S1
IN1
D1
S2
IN2
IN2
D2
S3
IN3
D3
S4
IN4
D4
S1
IN1
D1
S2
IN2
D2
S3
D3
S4
IN4
D4
SWITCHES SHOWN FOR A LOGIC "1" INPUT
IN4
D4
D3
S4
IN1
D1
S2
D2
S3
S1
2
ADG431
IN3
ADG432
ADG433
IN3
GENERAL DESCRIPTION
The ADG431, ADG432 and ADG433 are monolithic CMOS
devices comprising four independently selectable switches. They
are designed on an enhanced LC
2
MOS process which provides
low power dissipation yet gives high switching speed and low on
resistance.
The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. Fast switching speed coupled with high
signal bandwidth also make the parts suitable for video signal
switching. CMOS construction ensures ultralow power dissipa-
tion making the parts ideally suited for portable and battery
powered instruments.
The ADG431, ADG432 and ADG433 contain four indepen-
dent SPST switches. The ADG431 and ADG432 differ only in
that the digital control logic is inverted. The ADG431 switches
are turned on with a logic low on the appropriate control input,
while a logic high is required for the ADG432. The ADG433
has two switches with digital control logic similar to that of the
ADG431 while the logic is inverted on the other two switches.
Each switch conducts equally well in both directions when ON
and has an input signal range which extends to the supplies. In
the OFF condition, signal levels up to the supplies are blocked.
All switches exhibit break before make switching action for use
in multiplexer applications. Inherent in the design is low charge
injection for minimum transients when switching the digital inputs.
PRODUCT HIGHLIGHTS
1. Extended Signal Range
The ADG431, ADG432 and ADG433 are fabricated on an
enhanced LC
2
MOS process giving an increased signal range
which extends fully to the supply rails.
2. Ultralow Power Dissipation
3. Low R
ON
4. Break-Before-Make Switching
This prevents channel shorting when the switches are config-
ured as a multiplexer.
5. Single Supply Operation
For applications where the analog signal is unipolar, the
ADG431, ADG432 and ADG433 can be operated from a
single rail power supply. The parts are fully specified with a
single +12 V power supply and will remain functional with
single supplies as low as +5 V.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
ADG431/ADG432/ADG433–SPECIFICATIONS
1
Dual Supply
(V
Parameter
ANALOG SWITCH
Analog Signal Range
R
ON
R
ON
vs. V
D
(V
S
)
R
ON
Drift
R
ON
Match
LEAKAGE CURRENTS
Source OFF Leakage I
S
(OFF)
Drain OFF Leakage I
D
(OFF)
Channel ON Leakage I
D
, I
S
(ON)
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current
I
INL
or I
INH
C
IN
Digital Input Capacitance
DYNAMIC CHARACTERISTICS
2
t
ON
t
OFF
DD
= +15 V
10%, V
SS
= –15 V
10%, V
L
= +5 V
10%, GND = O V, unless otherwise noted)
B Versions
–40 C to
+25 C +85 C
V
DD
to V
SS
17
24
15
0.5
5
±
0.05
±
0.25
±
0.05
±
0.25
±
0.1
±
0.35
26
T Versions
–55 C to
+25 C +125 C
V
DD
to V
SS
17
24
15
0.5
5
±
0.05
±
0.25
±
0.05
±
0.25
±
0.1
±
0.35
27
Units
Test Conditions/Comments
V
Ω
typ
V
D
=
±
8.5 V, I
S
= –10 mA;
Ω
max
V
DD
= +13.5 V, V
SS
= –13.5 V
% typ
%/°C typ
% typ
V
D
= 0 V, I
S
= –10 mA
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA
typ
µA
max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
V
IN
= V
INL
or V
INH
V
DD
= +16.5 V, V
SS
= –16.5 V
V
D
=
±
15.5 V, V
S
= 15.5 V;
Test Circuit 2
V
D
=
±
15.5 V, V
S
= 15.5 V;
Test Circuit 2
V
D
= V
S
=
±
15.5 V;
Test Circuit 3
±
2
±
2
±
3
2.4
0.8
±
15
±
15
±
17
2.4
0.8
0.005
9
90
±
0.02
0.005
9
90
±
0.02
165
60
130
Break-Before-Make Time Delay, t
D
25
(ADG433 Only)
Charge Injection
OFF Isolation
Channel-to-Channel Crosstalk
C
S
(OFF)
C
D
(OFF)
C
D
, C
S
(ON)
POWER REQUIREMENTS
I
DD
I
SS
I
L
Power Dissipation
0.0001
0.1
0.2
0.0001
0.1
0.2
0.0001
0.1
0.2
7.7
5
68
85
9
9
35
25
60
175
145
5
68
85
9
9
35
pC typ
dB typ
dB typ
pF typ
pF typ
pF typ
V
DD
= +15 V, V
SS
= –15 V
R
L
= 300
Ω,
C
L
= 35 pF;
V
S
=
±
10 V; Test Circuit 4
R
L
= 300
Ω,
C
L
= 35 pF;
V
S
=
±
10 V; Test Circuit 4
R
L
= 300
Ω,
C
L
= 35 pF;
V
S1
= V
S2
= +10 V;
Test Circuit 5
V
S
= 0 V, R
S
= 0
Ω,
C
L
= 10 nF;
Test Circuit 6
R
L
= 50
Ω,
C
L
= 5 pF, f = 1 MHz;
Test Circuit 7
R
L
= 50
Ω,
C
L
= 5 pF, f = 1 MHz;
Test Circuit 8
f = 1 MHz
f = 1 MHz
f = 1 MHz
V
DD
= +16.5 V, V
SS
= –16.5 V
Digital Inputs = 0 V or 5 V
0.0001
0.1
0.2
0.0001
0.1
0.2
0.0001
0.1
0.2
7.7
µA
typ
µA
max
µA
typ
µA
max
µA
typ
µA
max
µW
max
NOTES
1
Temperature ranges are as follows: B Versions: –40
°C
to +85°C; T Versions: –55°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. B
ADG431/ADG432/ADG433
Single Supply
(V
Parameter
ANALOG SWITCH
Analog Signal Range
R
ON
R
ON
vs. V
D
(V
S
)
R
ON
Drift
R
ON
Match
LEAKAGE CURRENTS
Source OFF Leakage I
S
(OFF)
Drain OFF Leakage I
D
(OFF)
Channel ON Leakage I
D
, Is (ON)
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current
I
INL
or I
INH
C
IN
Digital Input Capacitance
DYNAMIC CHARACTERISTICS
2
t
ON
t
OFF
DD
= +12 V
10%, V
SS
= O V, V
L
= +5 V
B Versions
–40 C to
+25 C +85 C
0 V to V
DD
28
42
20
0.5
5
±
0.04
±
0.25
±
0.04
±
0.25
±
0.01
±
0.3
45
10%, GND = O V, unless otherwise noted)
T Versions
–55 C to
+25 C +125 C
0 V to V
DD
28
42
20
0.5
5
±
0.04
±
0.25
±
0.04
±
0.25
±
0.01
±
0.3
45
Units
Test Conditions/Comments
V
Ω
typ
0 < V
D
< 8.5 V, I
S
= –10 mA;
Ω
max
V
DD
= +10.8 V
% typ
%/°C typ
% typ
V
D
= 0 V, I
S
= –10 mA
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA
typ
µA
max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
V
IN
= V
INL
or V
INH
V
DD
= +13.2 V
V
D
= 12.2/1 V, V
S
= 1/12.2 V;
Test Circuit 2
V
D
= 12.2/1 V, V
S
= 1/12.2 V;
Test Circuit 2
V
D
= V
S
= +12.2 V/+1 V;
Test Circuit 3
±
2
±
2
±
3
2.4
0.8
±
15
±
15
±
17
2.4
0.8
0.005
9
165
±
0.01
0.005
9
165
±
0.01
240
60
115
Break-Before-Make Time Delay, t
D
25
(ADG433 Only)
Charge Injection
OFF Isolation
Channel-to-Channel Crosstalk
C
S
(OFF)
C
D
(OFF)
C
D
, C
S
(ON)
POWER REQUIREMENTS
I
DD
I
L
Power Dissipation
0.0001
0.03
0.1
0.0001
0.03
0.1
1.9
25
68
85
9
9
35
25
60
240
115
25
68
85
9
9
35
pC typ
dB typ
dB typ
pF typ
pF typ
pF typ
V
DD
= +12 V, V
SS
= 0 V
R
L
= 300
Ω,
C
L
= 35 pF;
V
S
= +8 V; Test Circuit 4
R
L
= 300
Ω,
C
L
= 35 pF;
V
S
= +8 V; Test Circuit 4
R
L
= 300
Ω,
C
L
= 35 pF;
V
S1
= V
S2
= +10 V;
Test Circuit 5
V
S
= 0 V, R
S
= 0
Ω,
C
L
= 10 nF;
Test Circuit 6
R
L
= 50
Ω,
C
L
= 5 pF, f = 1 MHz;
Test Circuit 7
R
L
= 50
Ω,
C
L
= 5 pF, f = 1 MHz;
Test Circuit 8
f = 1 MHz
f = 1 MHz
f = 1 MHz
V
DD
= +13.2 V
Digital Inputs = 0 V or 5 V
0.0001
0.03
0.1
0.0001
0.03
0.1
1.9
µA
typ
µA
max
µA
typ
µA
max
µW
max
V
L
= +5.25 V
NOTES
1
Temperature ranges are as follows: B Versions: –40
°C
to +85°C; T Versions: –55°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
Truth Table (ADG431/ADG432)
Truth Table (ADG433)
ADG431 In
0
1
REV. B
ADG432 In
1
0
Switch Condition
ON
OFF
–3–
Logic
0
1
Switch 1, 4
OFF
ON
Switch 2, 3
ON
OFF
ADG431/ADG432/ADG433
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25°C unless otherwise noted)
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
V
L
to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Analog, Digital Inputs
2
. . . . . . . . . . V
SS
– 2 V to V
DD
+ 2 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW
θ
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 76°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300°C
Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW
θ
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 117°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW
θ
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 77°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG431/ADG432/ADG433 features proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
(DIP/SOIC)
IN1
1
D1
2
S1
3
V
SS 4
16
IN2
15
D2
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
1
ADG431BN
ADG431BR
ADG431TQ
ADG431ABR
ADG432BN
ADG432BR
ADG432TQ
ADG432ABR
ADG433BN
ADG433BR
ADG433ABR
Temperature Range
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Options
2
N-16
R-16A
Q-16
R-16A
3
N-16
R-16A
Q-16
R-16A
3
N-16
R-16A
R-16A
3
13
V
DD
TOP VIEW
GND
5
(Not to Scale)
12
V
L
ADG431
ADG432
ADG433
14
S2
S4
6
D4
7
IN4
8
11
S3
10
D3
9
IN3
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to T grade part numbers.
2
N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); Q = Cerdip.
3
Trench isolated, latch-up proof parts. See Trench Isolation section.
TERMINOLOGY
Most positive power supply potential.
Most negative power supply potential in dual
V
SS
supplies. In single supply applications, it may be
connected to GND.
Logic power supply (+5 V).
V
L
GND
Ground (0 V) reference.
S
Source terminal. May be an input or output.
D
Drain terminal. May be an input or output.
IN
Logic control input.
Ohmic resistance between D and S.
R
ON
R
ON
vs. V
D
(V
S
) The variation in R
ON
due to a change in the ana-
log input voltage with a constant load current.
Change in R
ON
vs. temperature.
R
ON
Drift
Difference between the R
ON
of any two switches.
R
ON
Match
Source leakage current with the switch “OFF.”
I
S
(OFF)
Drain leakage current with the switch “OFF.”
I
D
(OFF)
Channel leakage current with the switch “ON.”
I
D
, I
S
(ON)
V
D
(V
S
)
Analog voltage on terminals D, S.
V
DD
C
S
(OFF)
C
D
(OFF)
C
D
, C
S
(ON)
C
IN
t
ON
t
OFF
t
D
Crosstalk
Off Isolation
Charge
Injection
“OFF” switch source capacitance.
“OFF” switch drain capacitance.
“ON” switch capacitance.
Input Capacitance to ground of a digital input.
Delay between applying the digital control input
and the output switching on.
Delay between applying the digital control input
and the output switching off.
“OFF” time or “ON” time measured between the
90% points of both switches, when switching
from one address state to another.
A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
A measure of unwanted signal coupling through an
“OFF” switch.
A measure of the glitch impulse transferred from the
digital input to the analog output during switching.
–4–
REV. B
Embedded System
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EEWORLD
