D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
CMOS, ±5 V/+5 V/+3 V, Triple SPDT Switch
ADG633
FEATURES
±2 V to ±6 V dual-supply operation
2 V to 12 V single-supply operation
Automotive temperature range: −40°C to +125°C
<0.2 nA leakage currents
52 Ω on resistance over full signal range
Rail-to-rail switching operation
16-lead LFCSP and TSSOP packages
Typical power consumption: <0.1 μW
TTL-/CMOS-compatible inputs
Package upgrades to 74HC4053 and MAX4053/MAX4583
FUNCTIONAL BLOCK DIAGRAM
S1B
D1
S1A
ADG633
S2A
D2
S2B
S3A
D3
S3B
LOGIC
APPLICATIONS
Automotive applications
Automatic test equipment
Data acquisition systems
Battery-powered systems
Communications systems
Audio and video signal routing
Relay replacement
Sample-and-hold systems
Industrial control systems
A0 A1 A2 EN
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 1.
GENERAL DESCRIPTION
The ADG633 is a low voltage CMOS device comprising three
independently selectable single-pole, double-throw (SPDT)
switches. The device is fully specified for ±5 V, +5 V, and +3 V
supplies. The ADG633 switches are turned on with a logic low
(or high) on the appropriate control input. Each switch conducts
equally well in both directions when on and has an input signal
range that extends to the supplies. An EN input is used to enable
or disable the device. When the device is disabled, all channels
are switched off.
The ADG633 is designed on an enhanced process that provides
lower power dissipation, yet is capable of high switching speeds.
Low power consumption and an operating supply range of 2 V
to 12 V make the ADG633 ideal for battery-powered, portable
instruments. All channels exhibit break-before-make switching
action, preventing momentary shorting when switching channels.
All digital inputs have 0.8 V to 2.4 V logic thresholds, ensuring
TTL/CMOS logic compatibility when using single +5 V or dual
±5 V supplies.
The ADG633 is available in a small, 16-lead TSSOP package
and a 16-lead, 4 mm × 4 mm LFCSP package.
PRODUCT HIGHLIGHTS
1.
Single- and dual-supply operation. The ADG633 offers
high performance and is fully specified and guaranteed
with ±5 V, +5 V, and +3 V supply rails.
Automotive temperature range: −40°C to +125°C.
Guaranteed break-before-make switching action.
Low power consumption, typically <0.1 μW.
Small, 16-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP
packages.
2.
3.
4.
5.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2009 Analog Devices, Inc. All rights reserved.
03275-001
ADG633
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual-Supply Operation ............................................................... 3
Single-Supply Operation ............................................................. 4
Absolute Maximum Ratings ............................................................6
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions..............................7
Typical Performance Characteristics ..............................................8
Terminology .................................................................................... 11
Test Circuits ..................................................................................... 12
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
11/09—Rev. 0 to Rev. A
Changes to Table 4 ............................................................................ 6
Added Table 5; Renumbered Sequentially .................................... 7
Changes to Table 6 ............................................................................ 7
Update Outline Dimensions ......................................................... 14
Changes to Ordering Guide .......................................................... 14
2/03—Revision 0: Initial Version
Rev. A | Page 2 of
16
ADG633
SPECIFICATIONS
DUAL-SUPPLY OPERATION
V
DD
= +5 V, V
SS
= −5 V, GND = 0 V, T
A
= −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, R
ON
On-Resistance Match
Between Channels, ΔR
ON
On-Resistance Flatness, R
FLAT(ON)
LEAKAGE CURRENTS
Source Off Leakage, I
S(OFF)
Drain Off Leakage, I
D(OFF)
Channel On Leakage, I
D(ON)
, I
S(ON)
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INL
or I
INH
Digital Input Capacitance, C
IN
DYNAMIC CHARACTERISTICS
1
t
TRANSITION
t
ON
(EN)
t
OFF
(EN)
Break-Before-Make Time Delay, t
BBM
Charge Injection
Off Isolation
Total Harmonic Distortion, THD + N
Channel-to-Channel Crosstalk
−3 dB Bandwidth
C
S(OFF)
C
D(OFF)
C
D(ON)
, C
S(ON)
POWER REQUIREMENTS
I
DD
I
SS
+25°C
B Version
−40°C to +85°C
Y Version
−40°C to +125°C
V
SS
to V
DD
52
75
0.8
1.3
9
12
±0.005
±0.2
±0.005
±0.2
±0.005
±0.2
±5
±5
2.4
0.8
0.005
±1
2
60
90
70
95
25
40
40
2
4
−90
0.025
−90
580
4
7
12
0.01
1
0.01
1
1
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
Test Conditions/Comments
V
DD
= +4.5 V, V
SS
= −4.5 V
V
S
= ±4.5 V, I
S
= 1 mA; see Figure 20
V
S
= ±4.5 V, I
S
= 1 mA; see Figure 20
V
S
= +3.5 V, I
S
= 1 mA
V
S
= +3.5 V, I
S
= 1 mA
V
DD
= +5 V, V
SS
= −5 V, V
S
= ±3 V, I
S
= 1 mA
V
DD
= +5 V, V
SS
= −5 V, V
S
= ±3 V, I
S
= 1 mA
V
DD
= +5.5 V, V
SS
= −5.5 V
V
D
= ±4.5 V, V
S
= +4.5 V; see Figure 21
V
D
= ±4.5 V, V
S
= +4.5 V; see Figure 21
V
D
= ±4.5 V, V
S
= + 4.5 V; see Figure 22
V
D
= ±4.5 V, V
S
= + 4.5 V; see Figure 22
V
D
= V
S
= ±4.5 V; see Figure 23
V
D
= V
S
= ±4.5 V; see Figure 23
90
100
1.8
13
2
14
±5
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
ns typ
V
IN
= V
INL
or V
INH
V
IN
= V
INL
or V
INH
R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 24
R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 24
R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 26
R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 26
R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 26
R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 26
R
L
= 300 Ω, C
L
= 35 pF, V
S1
= V
S2
= 3 V; see Figure 25
R
L
= 300 Ω, C
L
= 35 pF, V
S1
= V
S2
= 3 V; see Figure 25
V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 27
V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 27
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 28
R
L
= 600 Ω, 2 V p-p, f = 20 Hz to 20 kHz
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 30
R
L
= 50 Ω, C
L
= 5 pF; see Figure 29
f = 1 MHz
f = 1 MHz
f = 1 MHz
V
DD
= +5.5 V, V
SS
= −5.5 V
Digital inputs = 0 V or 5.5 V
Digital inputs = 0 V or 5.5 V
Digital inputs = 0 V or 5.5 V
Digital inputs = 0 V or 5.5 V
110
120
45
130
135
50
10
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
pC max
dB typ
% typ
dB typ
MHz typ
pF typ
pF typ
pF typ
μA typ
μA max
μA typ
μA max
Guaranteed by design; not subject to production test.
Rev. A | Page 3 of
16
ADG633
SINGLE-SUPPLY OPERATION
V
DD
= 5 V, V
SS
= 0 V, GND = 0 V, T
A
= −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, R
ON
On-Resistance Match
Between Channels, ΔR
ON
On-Resistance Flatness, R
FLAT(ON)
LEAKAGE CURRENTS
Source Off Leakage, I
S(OFF)
Drain Off Leakage, I
D(OFF)
Channel On Leakage, I
D(ON)
, I
S(ON)
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INL
or I
INH
Digital Input Capacitance, C
IN
DYNAMIC CHARACTERISTICS
1
t
TRANSITION
t
ON
(EN)
t
OFF
(EN)
Break-Before-Make Time Delay, t
BBM
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
C
S(OFF)
C
D(OFF)
C
D(ON)
, C
S(ON)
POWER REQUIREMENTS
I
DD
+25°C
B Version
−40°C to +85°C
Y Version
−40°C to +125°C
0 to V
DD
85
150
4.5
8
13
±0.005
±0.2
±0.005
±0.2
±0.005
±0.2
160
200
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
pC max
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
μA typ
μA max
Test Conditions/Comments
V
DD
= 4.5 V, V
SS
= 0 V
V
S
= 0 V to 4.5 V, I
S
= 1 mA; see Figure 20
V
S
= 0 V to 4.5 V, I
S
= 1 mA; see Figure 20
V
S
= +3.5 V, I
S
= 1 mA
V
S
= +3.5 V, I
S
= 1 mA
V
DD
= 5 V, V
SS
= 0 V, V
S
= 1.5 V to 4 V, I
S
= 1 mA
V
DD
= 5.5 V
V
S
= 1 V/4.5 V, V
D
= 4.5 V/1 V; see Figure 21
V
S
= 1 V/4.5 V, V
D
= 4.5 V/1 V; see Figure 21
V
S
= 1 V/4.5 V, V
D
= 4.5 V/1 V; see Figure 22
V
S
= 1 V/4.5 V, V
D
= 4.5 V/1 V; see Figure 22
V
S
= V
D
= 1 V or 4.5 V; see Figure 23
V
S
= V
D
= 1 V or 4.5 V; see Figure 23
9
14
10
16
±5
±5
±5
2.4
0.8
0.005
±1
2
100
150
100
150
25
35
90
0.5
1
−90
−90
520
5
8
12
0.01
1
V
IN
= V
INL
or V
INH
V
IN
= V
INL
or V
INH
190
190
45
220
220
50
10
R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 24
R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 24
R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 26
R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 26
R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 26
R
L
= 300 Ω, C
L
= 35 pF, V
S
= 3 V; see Figure 26
R
L
= 300 Ω, C
L
= 35 pF, V
S1
= V
S2
= 3 V; see Figure 25
R
L
= 300 Ω, C
L
= 35 pF, V
S1
= V
S2
= 3 V; see Figure 25
V
S
= 2.5 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 27
V
S
= 2.5 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 27
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 28
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 30
R
L
= 50 Ω, C
L
= 5 pF; see Figure 29
f = 1 MHz
f = 1 MHz
f = 1 MHz
V
DD
= 5.5 V
Digital inputs = 0 V or 5.5 V
Digital inputs = 0 V or 5.5 V
1
Guaranteed by design; not subject to production test.
Rev. A | Page 4 of
16
京公网安备 11010802033920号
EEWORLD
