November 2003
rev F
Versatile EMI Reduction IC
Features
FCC approved method of EMI attenuation
Provides up to 20 dB of EMI suppression
Generates a low EMI spread spectrum clock
of the input frequency
Optimized for 25 MHz to 60MHz input
frequency range
Internal loop filter minimizes external
components and board space
4 selectable spread ranges
SSON control pin for spread spectrum
enable and disable options
Characterizes to work with EMI-Lator®, EMC
simulation program.
Low cycle-to-cycle jitter
3.3 V or 5.0 V operating range
16 mA output drives
TTL or CMOS compatible outputs
Low power CMOS design
Available in 8 pin SOIC and TSSOP
Product Description
The P2041 is a selectable spread spectrum
frequency modulator designed specifically for PC
peripheral and embedded controller markets .The
P2041 reduces electromagnetic interference (EMI) at
Block Diagram
P2041A
the clock source which provides system wide
reduction of EMI of all clock dependent signals. The
P2041 allows significant system cost savings by
reducing the number of circuit board layers and
shielding that are traditionally required to pass EMI
regulations.
The P2041 uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all-digital method.
The P2041 modulates the output of a single PLL in
order to “spread” the bandwidth of a synthesized
clock and, more importantly, decreases the peak
amplitudes of its harmonics. This results in
significantly lower system EMI compared to the
typical narrow band signal produced by oscillators
and most frequency generators. Lowering EMI by
increasing a signal’s bandwidth is called “spread
spectrum clock generation”.
Applications
The P2041 is targeted towards the embedded
controller market and PC peripheral markets
including scanners, MFP’s, printers, PDA, IA , and
GPS devices.
Alliance Semiconductor
2575, Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
November 2003
rev F
Pin Configuration
P2041A
Pin Description
Pin#
1
2
3
4
5
6
7
8
ModOUT
SR0
VDD
O
I
P
Pin Name
XIN/CLK
XOUT
SR1
VSS
SSON
Type
I
I
I
P
I
Description
Connect to crystal or externally generated clock signal.
Connect to crystal. No connect if externally generated clock signal is used.
Digital logic input used to select Spreading Range (see Table 1). This pin
has an internal pull-up resistor.
Ground Connection. Connect to system ground.
Digital logic input used to enable Spread Spectrum function (Active Low).
Spread Spectrum function enable when low. This pin has an internal pull-
low resistor.
Spread Spectrum Clock Output.
Digital logic input used to select Spreading Range (see Table 1). This pin
has an internal pull-up resistor.
Connect to +3.3V or +5.0V
Table 1 - Spread Range Selection
FS0
0
0
1
1
SR0
0
1
0
1
Spreading Range
+/- 1.50%
+/- 2.50%
+/- 0.50%
+/- 1.00%
Input Frequency
(Fin/40)*34.72 KHz
(Fin/40)*34.72 KHz
(Fin/40)*34.72 KHz**
(Fin/40)*34.72 KHz**
Modulation rate
0
0
1
1
Versatile EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 9
November 2003
rev F
P2041A
Spread spectrum selection
Table 1 illustrates the possible spread spectrum options. The optimal setting should minimize system EMI to the
fullest without affecting system performance. The spreading is described as a percentage deviation of the center
frequency (Note: the center frequency is the frequency of the external reference input on CLKIN, Pin 1).
Example of a typical printer or scanner application that operates on a clock frequency of 40 MHz:
A spreading selection of SR1=1 and SR0=1 provides a percentage deviation of +/-1.00%* (see Table 1) of F
cen
.
This results in the frequency on ModOUT being swept from 40.40 MHz to 39.60 MHz at a modulation rate of
40/40*34.72=34.72 KHz (see Table 1). This particular example (see Figure below) given here is a common EMI
reduction method for scanners and has already been implemented by most of the leading manufacturers.
NOTE:
Spreading range selection varies from different system manufacturers and their designs. The spreading range of P2041 can be set
to +/-2.5% when working with certain scanner model.
P2041 Application Schematic for Flat-Bed Scanner
Versatile EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 9
November 2003
rev F
P2041A
EMC Software Simulation
By using Alliance Semiconductor’s proprietary EMC simulation software – EMI-lator®, radiated system level EMI
analysis can be made easier to allow a quantitative assessment on Alliance’s EMI reduction products. The
simulation engine of this EMC software has already been characterized to correlate with the electrical
characteristics of Alliance EMI reduction IC’s. The figure below is an example of the simulation result. Please
visit our web site at
www.alsc.comfor
information on how to obtain a free copy and demonstration of EMI-lator®.
Simulation Result from EMI-lator®
Versatile EMI Reduction IC
Notice: The information in this document is subject to change without notice.
4 of 9
November 2003
rev F
Absolute Maximum Ratings
Symbol
V
DD
, V
IN
T
STG
T
A
Parameter
Voltage on any pin with respect to GND
Storage temperature
Operating temperature
Rating
-0.5 to + 7.0
-65 to +125
0 to +70
P2041A
Unit
V
°C
°C
DC Electrical Characteristics
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
DD
I
CC
V
DD
Input Low Voltage
Input High Voltage
Input Low Current (pull-up resistor on inputs SR0, 1)
Input High Current (pull-down resistor on input SSON)
XOUT Output Low Current (@ 0.4V, V
DD
= 3.3V)
XOUT Output High Current (@ 2.5V, V
DD
= 3.3V)
Output Low Voltage (V
DD
=3.3V, I
OL
= 20 mA)
Output High Voltage (V
DD
=3.3V, I
OH
= 20 mA)
Static Supply Current
Dynamic Supply Current (3.3V and 15 pF loading)
Operating Voltage
Parameter
Min
GND – 0.3
2.0
-
-
-
-
-
2.5
-
7
2.7
Typ
-
-
-
-
3
3
-
-
0.6
8.6
3.3
Max
0.8
V
DD
+ 0.3
-35
35
-
-
0.4
-
-
10
5.5
Unit
V
V
µA
µA
mA
mA
V
V
mA
mA
V
AC Electrical Characteristics
Symbol
f
IN
t
LH
*
t
HL
*
t
JC
t
D
Parameter
Input Frequency when
Output rise time
(Measured at 0.8V to 2.0V)
Output fall time
(Measured at 0.8V to 2.0V)
Jitter (cycle to cycle)
Output duty cycle
Min
25
0.7
0.6
-
45
Typ
40
0.9
0.8
-
50
Max
60
1.1
1.0
360
55
Unit
MHz
ns
ns
ps
%
*t
LH
and t
HL
are measured into a capacitive load of 15pF
Versatile EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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