PCA9512A; PCA9512B
Level shifting hot swappable I
2
C-bus and SMBus bus buffer
Rev. 5 — 5 January 2011
Product data sheet
1. General description
The PCA9512A/B is a hot swappable I
2
C-bus and SMBus buffer that allows I/O card
insertion into a live backplane without corruption of the data and clock buses and includes
two dedicated supply voltage pins to provide level shifting between 3.3 V and 5 V systems
while maintaining the best noise margin for each voltage level. Either pin may be powered
with supply voltages ranging from 2.7 V to 5.5 V with no constraints on which supply
voltage is higher. Control circuitry prevents the backplane from being connected to the
card until a stop bit or bus idle occurs on the backplane without bus contention on the
card. When the connection is made, the PCA9512A/B provides bidirectional buffering,
keeping the backplane and card capacitances isolated.
The PCA9512A or PCA9512B can be used if the rise of V
CC
and V
CC2
is simultaneous,
but only the PCA9512B shall be used if the interval between rise of V
CC
and V
CC2
is not
simultaneous.
The PCA9512A/B rise time accelerator circuitry allows the use of weaker DC pull-up
currents while still meeting rise time requirements. The PCA9512A/B incorporates a digital
input pin that enables and disables the rise time accelerators on all four SDAn and SCLn
pins.
During insertion, the PCA9512A/B SDAn and SCLn pins are precharged to 1 V to
minimize the current required to charge the parasitic capacitance of the chip.
The incremental offset design of the PCA9510A/11A/12A/12B/13A/14A I/O drivers allow
them to be connected to another PCA9510A/11A/12A/12B/13A/14A device in series or in
parallel and to the I
2
C compliant side of static offset bus buffers, but not to the static offset
side of those bus buffers.
2. Features and benefits
Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and
SCL corruption during live board insertion and removal from multipoint backplane
systems
Compatible with I
2
C-bus Standard mode, I
2
C-bus Fast mode, and SMBus standards
Built-in
ΔV/Δt
rise time accelerators on all SDA and SCL lines (0.6 V threshold) with
ability to disable
ΔV/Δt
rise time accelerator through the ACC pin for lightly loaded
systems, requires the bus pull-up voltage and respective supply voltage (V
CC
or V
CC2
)
to be the same
5 V to 3.3 V level translation with optimum noise margin
High-impedance SDAn and SCLn pins for V
CC
or V
CC2
= 0 V
1 V precharge on all SDAn and SCLn pins
Supports clock stretching and multiple master arbitration and synchronization
NXP Semiconductors
PCA9512A; PCA9512B
Level shifting hot swappable I
2
C-bus and SMBus bus buffer
Operating power supply voltage range: 2.7 V to 5.5 V
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO8, TSSOP8 (MSOP8)
3. Applications
cPCI, VME, AdvancedTCA cards and other multipoint backplane cards that are
required to be inserted or removed from an operating system
4. Feature selection
Table 1.
Feature
Idle detect
High-impedance SDAn, SCLn pins for V
CC
= 0 V
Feature selection chart
PCA9510A PCA9511A PCA9512A/B PCA9513A PCA9514A
yes
yes
yes
yes
yes
-
-
yes
-
yes
-
yes
yes
yes
yes
-
-
yes
yes
-
yes
yes
yes
-
yes
yes
-
-
yes
yes
yes
yes
-
yes
yes
-
-
-
Rise time accelerator circuitry on SDAn and SCLn pins -
Rise time accelerator circuitry hardware disable pin for -
lightly loaded systems
Rise time accelerator threshold 0.8 V versus 0.6 V
improves noise margin
Ready open-drain output
Two V
CC
pins to support 5 V to 3.3 V level translation
with improved noise margins
1 V precharge on all SDAn and SCLn pins
-
yes
-
in only
92
μA
current source on SCLIN and SDAIN for PICMG -
applications
5. Ordering information
Table 2.
Ordering information
T
amb
=
−
40
°
C to +85
°
C
Type number
PCA9512AD
PCA9512BD
PCA9512ADP
PCA9512BDP
[1]
Topside
mark
PA9512A
PA9512B
9512A
9512B
Package
Name
SO8
TSSOP8
[1]
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
Also known as MSOP8.
Standard packing quantities and other packaging data are available at the NXP web site.
PCA9512A_PCA9512B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 5 January 2011
2 of 24
NXP Semiconductors
PCA9512A; PCA9512B
Level shifting hot swappable I
2
C-bus and SMBus bus buffer
6. Block diagram
PCA9512A/B
V
CC
2 mA
2 mA
V
CC2
ACC
SLEW RATE
DETECTOR
BACKPLANE-TO-CARD
CONNECTION
CONNECT
100 kΩ
RCH1
SLEW RATE
DETECTOR
SDAOUT
CONNECT
100 kΩ
RCH3
SDAIN
CONNECT
1 VOLT
PRECHARGE
100 kΩ
RCH2
2 mA
100 kΩ
RCH4
2 mA
ACC
SLEW RATE
DETECTOR
BACKPLANE-TO-CARD
CONNECTION
CONNECT
SLEW RATE
DETECTOR
ACC
SCLIN
SCLOUT
CONNECT
0.5
μA
STOP BIT AND
BUS IDLE
0.55V
CC
/
0.45V
CC
20 pF
0.55V
CC
/
0.45V
CC
UVLO
100
μs
DELAY
CONNECT
UVLO
CONNECT
RD
S
GND
QB
0.5 pF
002aab788
Fig 1.
Block diagram of PCA9512A/B
PCA9512A_PCA9512B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 5 January 2011
3 of 24
NXP Semiconductors
PCA9512A; PCA9512B
Level shifting hot swappable I
2
C-bus and SMBus bus buffer
7. Pinning information
7.1 Pinning
V
CC2
SCLOUT
SCLIN
GND
1
2
3
4
002aab789
8
V
CC
SDAOUT
SDAIN
ACC
V
CC2
SCLOUT
SCLIN
GND
1
2
3
4
002aab790
8
V
CC
SDAOUT
SDAIN
ACC
PCA9512AD
PCA9512BD
7
6
5
PCA9512ADP
PCA9512BDP
7
6
5
Fig 2.
Pin configuration for SO8
Fig 3.
Pin configuration for TSSOP8
7.2 Pin description
Table 3.
Symbol
V
CC2
SCLOUT
SCLIN
GND
ACC
Pin description
Pin
1
2
3
4
5
Description
Supply voltage for devices on the card I
2
C-bus. Connect pull-up resistors
from SDAOUT and SCLOUT to this pin.
serial clock output to and from the SCL bus on the card
serial clock input to and from the SCL bus on the backplane
ground supply; connect this pin to a ground plane for best results.
CMOS threshold digital input pin that enables and disables the rise time
accelerators on all four SDAn and SCLn pins. ACC enables all accelerators
when set to V
CC2
, and turns them off when set to GND.
serial data input to and from the SDA bus on the backplane
serial data output to and from the SDA bus on the card
supply voltage; from the backplane, connect pull-up resistors from SDAIN
and SCLIN to this pin.
SDAIN
SDAOUT
V
CC
6
7
8
8. Functional description
Refer to
Figure 1 “Block diagram of PCA9512A/B”.
8.1 Start-up
When the PCA9512A/B is powered up, either V
CC
or V
CC2
may rise first, within a short
time of each other and either may be more positive or they may be equal, however the
PCA9512A/B will not leave the undervoltage lockout or initialization state until both V
CC
and V
CC2
have gone above 2.5 V. If either V
CC
or V
CC2
drops below 2.0 V it will return to
the undervoltage lockout state.
Use of PCA9512B is required where the interval
between rise of V
CC
and V
CC2
is not simultaneous.
In the undervoltage lockout state
the connection circuitry is disabled, the rise time accelerators are disabled, and the
precharge circuitry is also disabled. After both V
CC
and V
CC2
are valid, independent of
which is higher, the PCA9512A/B enters the initialization state; during this state the 1 V
precharge circuitry is activated and pulls up the SDAn and SCLn pins to 1 V through
individual 100 kΩ nominal resistors. At the end of the initialization state the ‘Stop bit and
PCA9512A_PCA9512B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 5 January 2011
4 of 24
NXP Semiconductors
PCA9512A; PCA9512B
Level shifting hot swappable I
2
C-bus and SMBus bus buffer
bus idle’ detect circuit is enabled. When all the SDAn and SCLn pins have been HIGH for
the bus idle time or when all pins are HIGH and a STOP condition is seen on the SDAIN
and SCLIN pins, the connect circuitry is activated, connecting SDAIN to SDAOUT and
SCLIN to SCLOUT. The 1 V precharge circuitry is disabled when the connection is made,
unless the ACC pin is LOW; the rise time accelerators are enabled at this time also.
8.2 Connect circuitry
Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as
SCLIN and SCLOUT become identical, with each acting as a bidirectional buffer that
isolates the input bus capacitance from the output bus capacitance while communicating.
If V
CC
≠
V
CC2
, then a level shifting function is performed between input and output. A LOW
forced on either SDAIN or SDAOUT will cause the other pin to be driven to a LOW by the
PCA9512A/B. The same is also true for the SCLn pins. Noise between 0.7V
CC
and V
CC
on the SDAIN and SCLIN pins, and 0.7V
CC2
and V
CC2
on the SDAOUT and SCLOUT pins
is generally ignored because a falling edge is only recognized when it falls below 0.7V
CC
for SDAIN and SCLIN (or 0.7V
CC2
for SDAOUT and SCLOUT pins) with a slew rate of at
least 1.25 V/μs. When a falling edge is seen on one pin, the other pin in the pair turns on a
pull-down driver that is referenced to a small voltage above the falling pin. The driver will
pull the pin down at a slew rate determined by the driver and the load. The first falling pin
may have a fast or slow slew rate; if it is faster than the pull-down slew rate, then the initial
pull-down rate will continue until it is LOW. If the first falling pin has a slow slew rate, then
the second pin will be pulled down at its initial slew rate only until it is just above the first
pin voltage then they will both continue down at the slew rate of the first.
Once both sides are LOW they will remain LOW until all the external drivers have stopped
driving LOWs. If both sides are being driven LOW to the same (or nearly the same) value
by external drivers, which is the case for clock stretching and is typically the case for
acknowledge, and one side external driver stops driving, that pin will rise and rise above
the nominal offset voltage until the internal driver catches up and pulls it back down to the
offset voltage. This bounce is worst for low capacitances and low resistances, and may
become excessive. When the last external driver stops driving a LOW, that pin will bounce
up and settle out just above the other pin as both rise together with a slew rate determined
by the internal slew rate control and the RC time constant. As long as the slew rate is at
least 1.25 V/μs, when the pin voltage exceeds 0.6 V, the rise time accelerator circuits are
turned on and the pull-down driver is turned off. If the ACC pin is LOW, the rise time
accelerator circuits will be disabled, but the pull-down driver will still turn off.
8.3 Maximum number of devices in series
Each buffer adds about 0.1 V dynamic level offset at 25
°C
with the offset larger at higher
temperatures. Maximum offset (V
offset
) is 0.150 V with a 10 kΩ pull-up resistor. The LOW
level at the signal origination end (master) is dependent upon the load and the only
specification point is the I
2
C-bus specification of 3 mA will produce V
OL
< 0.4 V, although if
lightly loaded the V
OL
may be ~0.1 V. Assuming V
OL
= 0.1 V and V
offset
= 0.1 V, the level
after four buffers would be 0.5 V, which is only about 0.1 V below the threshold of the
rising edge accelerator (about 0.6 V). With great care a system with four buffers may
work, but as the V
OL
moves up from 0.1 V, noise or bounces on the line will result in firing
the rising edge accelerator thus introducing false clock edges. Generally it is
recommended to limit the number of buffers in series to two, and to keep the load light to
minimize the offset.
PCA9512A_PCA9512B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 5 January 2011
5 of 24
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