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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
μ
PA2354
DUAL N-CHANNEL MOSFET
DESCRIPTION
The
μ
PA2354 is a Dual N-channel MOSFET designed for
Lithium-Ion battery protection circuit.
Ecologically Flip chip MOSFET for Lithium-Ion battery Protection
(EFLIP).
1.33
±
0.02
OUTLINE DRAWING (Unit: mm)
TOP VIEW
1.33
±
0.02
BOTTOM VIEW
0.65
FEATURES
•
Monolithic Dual MOSFET
Connecting the Drains on the circuit board is not required
because the Drains of the FET1 and the FET2 are internally
connected.
1.8 V drive available and low on-state resistance
R
SS(on)1
= 42.0 mΩ MAX. (V
GS
= 4.5 V, I
S
= 2.0 A)
R
SS(on)2
= 49.0 mΩ MAX. (V
GS
= 3.1 V, I
S
= 2.0 A)
R
SS(on)3
= 57.0 mΩ MAX. (V
GS
= 2.5 V, I
S
= 2.0 A)
R
SS(on)4
= 99.0 mΩ MAX. (V
GS
= 1.8 V, I
S
= 2.0 A)
Built-in G-S protection diode against ESD
Pb-free Bump
G2
S2
0.65
G1
S1
•
1-pin index mark S1
Dot area (For in-house)
// 0.1 S
4 -
φ
0.37
S1: Source 1
G1: Gate 1
G2: Gate 2
S2: Source 2
S
0.2
±
0.02
0.28
±
0.03
0.08 S
•
•
ORDERING INFORMATION
PART NUMBER
PACKAGE
Note
μ
PA2354T1G-E4-A
4-pin EFLIP
Note
Pb-free (This product does not contain Pb in the external electrode and other parts.)
Remark
"-E4" indicates the unit orientation (E4 only).
EQUIVALENT CIRCUIT
FET1
FET2
Gate 2
Gate
Protection
Diode
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C)
Source to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
SS
= 0 V)
Note1
Source Current (DC)
Note2
Source Current (pulse)
Note1
Total Power Dissipation (2 units)
Channel Temperature
Storage Temperature
V
SSS
V
GSS
I
S(DC)
I
S(pulse)
P
T
T
ch
T
stg
24
±8
±4.0
±33
0.75
150
−55
to +150
V
V
A
A
W
°C
°C
Gate 1
Source 1
Body Diode
Source 2
Notes 1.
Mounted on BT resin board of 40.5 mm x 25 mm x 1.5 mmt
2.
PW
≤
100
μ
s, Duty Cycle
≤
1%
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD. When this
device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage
may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G19316EJ1V0DS00 (1st edition)
Date Published February 2009 NS
Printed in Japan
2009
FPGA/CPLD
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