MS76542-35GC datasheet, PDF - EEWORLD Datasheet

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MS76542-35GC: DescriptionBi-Directional FIFO, 512X36, 35ns, Synchronous, CMOS; Categorystorage storage; File Size51KB，1 Pages; ManufacturerMosel Vitelic Corporation ( MVC ); Websitehttp://www.moselvitelic.com

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MS76542-35GC Overview

Bi-Directional FIFO, 512X36, 35ns, Synchronous, CMOS

MS76542-35GC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Mosel Vitelic Corporation ( MVC )
package instruction	PGA, PGA(UNSPEC)
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	35 ns
Other features	RETRANSMIT
period time	35 ns
JESD-30 code	R-CPGA-P
JESD-609 code	e0
memory density	18432 bit
Memory IC Type	BI-DIRECTIONAL FIFO
memory width	36
Number of functions	1
word count	512 words
character code	512
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512X36
Output characteristics	3-STATE
Exportable	YES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA(UNSPEC)
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
power supply	5 V
Certification status	Not Qualified
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal location	PERPENDICULAR

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MS76542-35GC Related Products

	MS76542-35GC	MS76542-30GC	MS76542-25GC
Description	Bi-Directional FIFO, 512X36, 35ns, Synchronous, CMOS	Bi-Directional FIFO, 512X36, 30ns, Synchronous, CMOS	Bi-Directional FIFO, 512X36, 25ns, Synchronous, CMOS
Is it Rohs certified?	incompatible	incompatible	incompatible
Maker	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )
package instruction	PGA, PGA(UNSPEC)	PGA, PGA(UNSPEC)	PGA, PGA(UNSPEC)
Reach Compliance Code	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99
Maximum access time	35 ns	30 ns	25 ns
Other features	RETRANSMIT	RETRANSMIT	RETRANSMIT
period time	35 ns	30 ns	25 ns
JESD-30 code	R-CPGA-P	R-CPGA-P	R-CPGA-P
JESD-609 code	e0	e0	e0
memory density	18432 bit	18432 bit	18432 bit
Memory IC Type	BI-DIRECTIONAL FIFO	BI-DIRECTIONAL FIFO	BI-DIRECTIONAL FIFO
memory width	36	36	36
Number of functions	1	1	1
word count	512 words	512 words	512 words
character code	512	512	512
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C
organize	512X36	512X36	512X36
Output characteristics	3-STATE	3-STATE	3-STATE
Exportable	YES	YES	YES
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA	PGA	PGA
Encapsulate equivalent code	PGA(UNSPEC)	PGA(UNSPEC)	PGA(UNSPEC)
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL
power supply	5 V	5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified
Nominal supply voltage (Vsup)	5 V	5 V	5 V
surface mount	NO	NO	NO
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG	PIN/PEG	PIN/PEG
Terminal location	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR

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