32Mx64 bits
Unbuffered DDR SO-DIMM
HYMD532M646(L)6-K/H/L
DESCRIPTION
Preliminary
Hynix HYMD532M646(L)6-K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline
Dual In-Line Memory Modules (SO-DIMMs) which are organized as 32Mx64 high-speed memoryarrays. Hynix
HYMD532M646(L)6-K/H/L series consists of four 32Mx16 DDR SDRAM in 400mil TSOP II packages on a 200pin
glass-epoxy substrate. Hynix HYMD532M646(L)6-K/H/L series provide a high performance 8-byte interface in
67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD532M646(L)6-K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous oper-
ations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are
latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All
input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD532M646(L)6-K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is
implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
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256MB (32M x 64) Unbuffered DDR SO-DIMM
based on 32Mx16 DDR SDRAM
JEDEC Standard 200-pin small outline dual in-line
memory module (SO-DIMM)
2.5V +/- 0.2V VDD and VDDQ Power supply
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
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Data inputs on DQS centers when write (centered
DQ)
Data strobes synchronized with output data for read
and input data for write
Programmable CAS Latency 1.5 / 2 / 2.5 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
tRAS Lock-out function supported
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
•
ORDERING INFORMATION
Part No.
HYMD532M646(L)6-K
HYMD532M646(L)6-H
HYMD532M646(L)6-L
V
DD
=2.5V
V
DDQ
=2.5V
Power Supply
Clock Frequency
133MHz(*DDR266A)
133MHz(*DDR266B)
125MHz(*DDR200)
Interface
Form Pactor
200pin Unbuffered SO-DIMM
67.6mm x 31.75mm x 3.8mm
SSTL_2
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1/May. 02
1
HYMD532M646(L)6-K/H/L
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
o
C
o
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to V
SS
Voltage on V
DD
relative to V
SS
Voltage on V
DDQ
relative to V
SS
Output Short Circuit Current
Power Dissipation
Soldering Temperature Þ Time
T
A
T
STG
V
IN
, V
OUT
V
DD
V
DDQ
I
OS
P
D
T
SOLDER
0 ~ 70
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
8
260 / 10
C
V
V
V
mA
W
o
C / Sec
Note :
Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Termination Voltage
Reference Voltage
V
DD
V
DDQ
V
IH
V
IL
V
TT
V
REF
2.3
2.3
V
REF
+ 0.15
-0.3
V
REF
- 0.04
1.15
2.5
2.5
-
-
V
REF
1.25
2.7
2.7
V
DDQ
+ 0.3
V
REF
- 0.15
V
REF
+ 0.04
1.35
V
V
V
V
V
V
3
2
1
Note :
1. V
DDQ
must not exceed the level of V
DD
.
2. V
IL
(min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of V
REF
is approximately equal to 0.5V
DDQ
.
AC OPERATING CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
Parameter
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CK and /CK inputs
Input Crossing Point Voltage, CK and /CK inputs
V
IH(AC)
V
IL(AC)
V
ID(AC)
V
IX(AC)
V
REF
+ 0.31
V
REF
- 0.31
0.7
0.5*V
DDQ
-0.2
V
DDQ
+ 0.6
0.5*V
DDQ
+0.2
V
V
V
V
1
2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Rev. 0.1/May. 02
4
HYMD532M646(L)6-K/H/L
AC OPERATING TEST CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to VSS = 0V)
Parameter
Value
Unit
Reference Voltage
Termination Voltage
AC Input High Level Voltage (V
IH
, min)
AC Input Low Level Voltage (V
IL
, max)
Input Timing Measurement Reference Level Voltage
Output Timing Measurement Reference Level Voltage
Input Signal maximum peak swing
Input minimum Signal Slew Rate
Termination Resistor (R
T
)
Series Resistor (R
S
)
Output Load Capacitance for Access Time Measurement (C
L
)
V
DDQ
x 0.5
V
DDQ
x 0.5
V
REF
+ 0.31
V
REF
- 0.31
V
REF
V
TT
1.5
1
50
25
30
V
V
V
V
V
V
V
V/ns
W
W
pF
Rev. 0.1/May. 02
5
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