82562EP 10/100 Mbps Platform LAN
Connect (PLC)
Networking Silicon
Datasheet
Product Features
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IEEE 802.3 10BASE-T/100BASE-TX
compliant physical layer interface
IEEE 802.3u Auto-Negotiation support
Digital Adaptive Equalization control
Link status interrupt capability
XOR tree mode support
3-port LED support (speed, link and
activity)
10BASE-T auto-polarity correction
Alert on LAN functionality
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Diagnostic loopback mode
1:1 transmit transformer ratio support
Low power (less than 300 mW in active
transmit mode)
Reduced power in “unplugged mode” (less
than 50 mW)
Automatic detection of “unplugged mode”
3.3 V device
Lead-free
1
64-pin Plastic Ball Grid Array
Package for both leaded and lead-free
designs. (Devices that are lead-free are
marked with a circled “e1” and have the
product code prefix: PCxxxxxx).
This device is lead-free. That is, lead has not been intentionally added, but lead may still exist
as an impurity at <1000 ppm. The Material Declaration Data Sheet, which includes lead
impurity levels and the concentration of other Restriction on Hazardous Substances (RoHS)-
banned materials, is available at:
ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks
1
In addition, this device has been tested and conforms to the same parametric specifications as
previous versions of the device.
For more information regarding lead-free products from Intel Corporation, contact your Intel
Field Sales representative.
Revision 2.0
September 2005
Revision History
Revision
1.0
1.4
1.5
1.6
2.0
Revision Date
August 2000
May 2001
October 2001
December 2003
September 2005
Initial release (Intel Secret).
Finialized signal descriptions and pinouts.
Changed document status to Intel Confidential - Controlled Access.
Removed confidential status.
Updated or new revision information includes:
•
•
•
•
•
Lead-free information.
Product codes.
Bias reference resistor values (RBIAS 10 and RBIAS 100).
Crystal input/output clock values.
Signal termination section.
Description
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are
not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82562EP PLC may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © 2005, Intel Corporation
* Other brands and names are the property of their respective owners.
Datasheet
Networking Silicon — 82562EP
Contents
1.0
1.1
1.2
1.3
2.0
2.1
2.2
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
4.0
4.1
4.1.1
4.1.2
5.0
5.1
5.2
6.0
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
7.0
7.1
7.1.1
Introduction......................................................................................................................... 1
Overview ...................................................................................................................... 1
References................................................................................................................... 1
Product Codes ............................................................................................................. 1
82562EP Architectural Overview........................................................................................ 3
LAN Connect Interface.................................................................................................3
Hardware Configuration ............................................................................................... 4
82562EP Signal Descriptions............................................................................................. 5
Signal Type Definitions ............................................................................................... 5
Twisted Pair Ethernet (TPE) Pins ............................................................................... 5
External Bias Pins ....................................................................................................... 5
Clock Pins ................................................................................................................... 6
Platform LAN Connect Interface Pins ......................................................................... 6
LED Pins .....................................................................................................................7
Miscellaneous Control Pins ......................................................................................... 7
Power and Ground Connections ................................................................................. 8
Signal Terminations............................................................................................................ 9
Terminating Resistors .................................................................................................. 9
Termination Plane................................................................................................10
Termination Plane Capacitance...........................................................................10
82562EP Test Port Functionality......................................................................................11
Asynchronous Test Mode ..........................................................................................11
Test Function Description ..........................................................................................11
Electrical and Timing Specifications.................................................................................13
Absolute Maximum Ratings .......................................................................................13
DC Characteristics ....................................................................................................13
X1 Clock DC Specifications ................................................................................13
LAN Connect Interface DC Specifications ..........................................................14
LED DC Specifications .......................................................................................14
10BASE-T Voltage and Current DC Specifications ............................................14
100BASE-TX Voltage and Current DC Specifications ........................................15
Package and Pinout Information ......................................................................................17
Package Information ..................................................................................................17
82562EP Pin Assignments .................................................................................19
Datasheet
iii
82562EP — Networking Silicon
Figures
1
2
3
4
5
6
82562EP PLC Block Diagram ............................................................................... 3
82562EP PLC 10/100 Mbps Ethernet Solution ..................................................... 3
Termination Resistors Placement (Integrated Magnetics Solution) ...................... 9
Dimension Diagram for the 82562EP 64-pin PBGA (1 of 2) ............................... 17
Dimension Diagram for the 82562EP 64-pin PBGA (2 of 2) ............................... 18
82562EP Pinout Diagram.................................................................................... 20
Tables
1
2
3
4
5
6
7
8
9
10
11
82562EP Hardware Configuration ........................................................................ 4
XOR Tree Chain Order ....................................................................................... 11
General DC Specifications .................................................................................. 13
X1 Clock DC Specifications ................................................................................ 13
LAN Connect Interface DC Specifications .......................................................... 14
LED DC Specifications........................................................................................ 14
10BASE-T Transmitter ........................................................................................ 14
10BASE-T Receiver ............................................................................................ 15
100BASE-TX Transmitter.................................................................................... 15
100BASE-TX Receiver........................................................................................ 15
82562EP Pin Assignments.................................................................................. 19
iv
Datasheet
Networking Silicon — 82562EP
1.0
1.1
Introduction
Overview
The Intel® 82562EP is a highly-integrated Platform LAN Connect (PLC) device designed for 10 or
100 Mbps Ethernet systems. It is based on the IEEE 10BASE-T and 100BASE-TX standards. The
IEEE 802.3u standard for 100BASE-TX defines networking over two pairs of Category 5
unshielded twisted pair cable or Type 1 shielded twisted pair cable.
The 82562EP complies with the IEEE 802.3u Auto-Negotiation standard and the IEEE 802.3x Full
Duplex Flow Control standard. The 82562EP also includes a PHY interface compliant to the
current PLC interface.
1.2
References
•
IEEE 802.3 Standard for Local and Metropolitan Area Networks, Institute of Electrical and
Electronics Engineers.
•
LAN Connect Interface Specification. Intel Corporation.
•
I/O Control Hub 2, 3, and 4 EEPROM Map and Programming Information. Intel Corporation.
Programming information can be obtained through your local Intel representatives.
1.3
Product Codes
The product ordering code for a lead-free device is: PC82562EP.
The product ordering code for a leaded device is: RC82562EP.
Datasheet
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