Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
[2]
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
5V
±
10%
5V
±
10%
Notes:
1. The Voltage on any input or I/O pin cannot exceed the power pin during
power-up.
2. T
A
is the “instant on” case temperature.
Document #: 38-06003 Rev. *A
Page 3 of 23
CY7C455
CY7C456
CY7C457
Pin Definitions
Signal Name
D
0
−
17
I/O
I
Description
Data Inputs: When the FIFO is not full and ENW is active, CKW (rising edge) writes data (D
0
−
17
) into
the FIFO’s memory. If MR is asserted at the rising edge of CKW, data is written into the FIFO’s
programming register. D
8
,
17
are ignored if the device is configured for parity generation.
Data Outputs: When the FIFO is not empty and ENR is active, CKR (rising edge) reads data (Q
0
−
7
,
Q
9
−
16
) out of the FIFO’s memory. If MR is active at the rising edge of CKR, data is read from the
programming register.
Function varies according to mode:
Parity disabled – same function as Q
0
−
7
and Q
9
−
16
Parity enabled, generation – parity generation bit (PG
x
)
Parity enabled, check – Parity Error Flag (PE
x
)
Enable Write: Enables the CKW input (for both non-program and program modes).
Enable Read: Enables the CKR input (for both non-program and program modes).
Write Clock: The rising edge clocks data into the FIFO when ENW is LOW; updates Half Full, Almost
Full, and Full flag states. When MR is asserted, CKW writes data into the program register.
Read Clock: The rising edge clocks data out of the FIFO when ENR is LOW; updates the Empty and
Almost Empty flag states. When MR is asserted, CKR reads data out of the program register.
Half Full Flag: Synchronized to CKW.
Empty or Full Flag: E is synchronized to CKR; F is synchronized to CKW.
Dual-Mode Pin:
Not Cascaded – programmable Almost Full is synchronized to CKW; Programmable Almost Empty is
synchronized to CKR.
Cascaded – expansion out signal, connected to XI of next device.
Expansion-In Pin:
Not Cascaded – XI is tied to V
SS
.
Cascaded – expansion Input, connected to XO of previous device.
First Load/Retransmit Pin:
Cascaded – the first device in the daisy chain will have FL tied to V
SS
; all other devices will have FL tied
to V
CC
(Figure
1).
Not Cascaded – tied to V
CC
.
Retransmit function is also available in standalone mode by strobing RT.
Master Reset: Resets device to empty condition.
Non-Programming Mode: Program register is reset to default condition of no parity and PAFE active at
16 or less locations from Full/Empty.
Programming Mode: Data present on D
0 - 9,10, or 11
and D
15-17
is written into the programmable register
on the rising edge of CKW. Program register contents appear on Q
0 - 9,10, or 11
and Q
15-17
after the rising
edge of CKR.
Output Enable for Q
0
−
7
, Q
9
−
16
, Q
8
/PG1/PE1 and Q
17
/PG2/PE2 pins.
Q
0
−
7
Q
9
−
16
Q
8
/PG1/PE1
Q
17
/PG2/PE2
O
O
ENW
ENR
CKW
CKR
HF
E/F
PAFE/XO
I
I
I
I
O
O
O
XI
I
FL/RT
I
MR
I
OE
I
Document #: 38-06003 Rev. *A
Page 4 of 23
CY7C455
CY7C456
CY7C457
Electrical Characteristics
Over the Operating Range
7C455/6/7–
12
Parameter
V
OH
V
OL
V
IH[3]
V
IL[3]
I
IX
I
OS[4]
I
OZL
I
OZH
I
CC1[5]
I
CC2[6]
I
SB[7]
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Current
Output Short
Circuit Current
Output OFF, High Z
Current
Operating Current
Operating Current
Standby Current
V
CC
= Max.
V
CC
= Max., V
OUT
= GND
OE > V
IH
, V
SS
< V
O
< V
CC
V
CC
= Max.,
I
OUT
= 0 mA
V
CC
= Max.,
I
OUT
= 0 mA
V
CC
= Max.,
I
OUT
= 0 mA
Com’l
Ind
Com’l
Ind
Com’l
Ind
Test Conditions
V
CC
= Min., I
OH
= –2.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.5
–10
–90
–10
+10
160
180
90
100
40
40
Min.
2.4
0.4
V
CC
0.8
+10
2.2
–0.5
–10
–90
–10
+10
160
180
90
100
40
40
Max
7C455/6/7– 7C455/6/7– 7C455/6/7–
14
20
30
Min.
2.4
0.4
V
CC
0.8
+10
2.2
–0.5
–10
–90
–10
+10
140
160
90
100
40
40
Max
Min.
2.4
0.4
V
CC
0.8
+10
2.2
–0.5
–10
–90
–10
+10
120
140
90
100
40
40
Max
Min.
2.4
0.4
V
CC
0.8
+10
Max
Unit
V
V
V
V
µA
mA
µA
mA
mA
mA
mA
mA
mA
Capacitance
[8]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 5.0V
Max.
10
12
Unit
pF
pF
AC Test Loads and Waveforms
[9, 10, 11, 12, 13]
R1 500Ω
5V
OUTPUT
C
L
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
200Ω
OUTPUT
R2
333Ω
3.0V
GND
≤
3 ns
ALL INPUT PULSES
90%
10%
90%
10%
≤
3 ns
c455-5
c455-4
2V
Notes:
3. The V
IH
and V
IL
specifications apply for all inputs except XI. The XI pin is not a TTL input. It is connected to either XO of the previous device or V
SS
.
4. Test no more than one output at a time for not more than one second.
5. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency (f
MAX
), while data inputs
switch at f
MAX
/2. Outputs are unloaded.
6. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz.
Outputs are unloaded.
7. All input signals are connected to V
CC
. All outputs are unloaded. Read and write clocks switch at maximum frequency (f
MAX
).
8. Tested initially and after any design or process changes that may affect these parameters.
9. C
L
= 30 pF for all AC parameters except for t
OHZ
.
10. C
L
= 5 pF for t
OHZ
.
11. All AC measurements are referenced to 1.5V except t
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