NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface
PRELIMINARY
August 1999
NM24C65U
64K-Bit Serial EEPROM with Write Protect
2-Wire Bus Interface
General Description:
The NM24C65U is a 64K (65,536) bit serial interface CMOS
EEPROM (Electrically Erasable Programmable Read-Only
Memory). This device fully conforms to the
Extended
I
2
C™ 2-wire
protocol which uses Clock (SCL) and Data I/O (SDA) pins to
synchronously clock data between the "master" (for example a
microprocessor) and the "slave" (the EEPROM device). In addi-
tion, the serial interface allows a minimal pin count packaging
designed to simplify PC board layout requirements and offers the
designer a variety of low voltage and low power options.
NM24C65U incorporates a hardware "Write Protect" feature, by
which the upper half of the memory can be disabled against
programming by connecting the WP pin to V
CC
. This section of
memory then effectively becomes a ROM (Read-Only Memory)
and can no longer be programmed as long as WP pin is connected
to V
CC
.
Fairchild EEPROMs are designed and tested for applications requir-
ing high endurance, high reliability and low power consumption for a
continuously reliable non-volatile solution for all markets.
Functions
I
I
2
C™ compatible interface
I
65,536 bits organized as 8,192 x 8
I
100 KHz or 400 KHz operation
I
Extended 2.7V – 5.5V operating voltage
I
Self timed programming cycle (6ms typical)
I
"Programming complete" indicated by ACK polling
I
Memory "Upper Block" Write Protect pin
Features
I
The I
2
C™ interface allows the smallest I/O pincount of any
EEPROM interface
I
32 byte page write mode to minimize total write time per byte
I
Low V
CC
programming lockout (3.8V)
—
"H" option (Standard V
CC
range) parts only
I
Typical 200µA active current (I
CCA
)
I
Typical 1µA standby current (I
SB
) for "L" devices and 0.1µA
standby current for "LZ" devices
I
Endurance: Up to 1,000,000 data changes
I
Data retention greater than 40 years
Block Diagram
VCC
WP
SDA
START
STOP
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
LOAD
A2
A1
A0
WORD
ADDRESS
COUNTER
INC
WRITE
LOCKOUT
START CYCLE
H.V. GENERATION
TIMING &CONTROL
SCL
XDEC
E2PROM
ARRAY
R/W
YDEC
CK
DIN
DATA REGISTER
DOUT
I
2
C™ is a registered trademark of Philips Electronics N.V.
DS800012-1
© 1999 Fairchild Semiconductor Corporation
NM24C65U Rev. B.1
1
www.fairchildsemi.com
NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface
AC Conditions of Test
Input Pulse Levels
Input Rise and Fall Times
Input & Output Timing Levels
Output Load
V
CC
x 0.1 to V
CC
x 0.9
10 ns
V
CC
x 0.5
1 TTL Gate and C
L
= 100 pF
Read and Write Cycle Limits (Standard and Low V
CC
Range - 2.7V-5.5V)
Symbol
f
SCL
T
I
Parameter
SCL Clock Frequency
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum V
IN
Pulse width)
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time - NM24C65U
- NM24C65UL, NM24C65ULZ
100 KHz
Min
Max
100
100
0.3
4.7
4.0
4.7
4.0
4.7
0
250
1
300
4.7
300
10
15
3.5
400 KHz
Min
Max
400
50
0.1
1.3
0.6
1.5
0.6
0.6
0
100
0.3
300
0.6
50
10
15
0.9
Units
KHz
ns
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
DH
t
WR
(Note 3)
Note 3:
The write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
NM24C65U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address
4
NM24C65U Rev. B.1
www.fairchildsemi.com
NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface
Bus Timing
tF
tHIGH
tLOW
SCL
tLOW
tR
SDA
SDA
OUT
BACKGROUND INFORMATION (IIC Bus)
As mentioned, the IIC bus allows synchronous bidirectional commu-
nication between Transmitter/Receiver using the SCL (clock) and
SDA (Data I/O) lines. All communication must be started with a valid
START condition, concluded with a STOP condition and acknowl-
edged by the Receiver with an ACKNOWLEDGE condition.
In addition, since the IIC bus is designed to support other devices
such as RAM, EPROM, etc., the device type identifier string, or
slave address, must follow the START condition. For EEPROMs,
the first 4-bits of the slave address is '1010'. This is then followed
by the device selection bits A2, A1 and A0.The final bit in the slave
address determines the type of operation performed (READ/
WRITE). A "1" signifies a READ while a "0" signifies a WRITE. The
slave address is then followed by two bytes that define the word
address, which is then followed by the data byte.
The EEPROMs on the IIC bus may be configured in any manner
required, providing the total memory addressed does not exceed
4M bits in the Extended IIC protocol. EEPROM memory address-
ing is controlled by hardware configuring the A2, A1, and A0 pins
(Device Address pins) with pull-up or pull-down resistors. ALL
UNUSED PINS MUST BE GROUNDED (tied to V
SS
).
Addressing an EEPROM memory location involves sending a
command string with the following information:
[DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK AD-
DRESS]-[BYTE ADDRESS]
;;
tSU:STA
tHD:STA
IN
tHD:DAT
tSU:DAT
tSU:STO
tBUF
tDH
tAA
DS800012-3
Pin Description
SERIAL CLOCK (SCL)
The SCL input is used to clock all data into and out of the device.
SERIAL DATA (SDA)
SDA is a biderectional pin used to transfer data into and out of the
device. It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs.
Device Address Inputs (A0, A1, A2)
Device address pins A0, A1, and A2 are connected to V
CC
or V
SS
to
configure the EEPROM address for multiple device configuration. A
total of eight different devices can be attached to the same SDA bus.
Write Protection (WP)
If WP is tied to V
CC
, program WRITE operations onto the upper half
of the memory will not be executed. READ operations are always
available.
If WP is tied to V
SS
, normal memory operation is enabled, READ/
WRITE over the entire bit memory array.
This feature allows the user to assign the upper half of the memory
as ROM which can be protected against accidental programming
writes. When WRITE is disabled, slave address and word address
will be acknowledged but data will not be acknowledged.
Definitions
Word
Page
8 bits (byte) of data
32 sequential addresses (one byte each) that
may be programmed during a "Page Write"
programming cycle.
Any IIC device CONTROLLING the transfer
of data (such as a microcontroller).
Device being controlled (EEPROMS are
always considered Slaves).
Device currently SENDING data on the bus
(may be either a Master or Slave).
Device currently RECEIVING data on the bus
(Master or Slave).
Device Operation
The NM24C65Uxxx supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the bus as a
transmitter and the receiving devices as the receiver. The device
controlling the transfer is the master and the device that is controlled
is the slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations. There-
fore, the NM24C65Uxxx is considered a slave in all applications.
Master
Slave
Transmitter
Receiver
CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH and reserved for indicating
start and stop conditions.
Refer to Figures 2 and 3.
START CONDITION
All commands are preceded by the start condition, which is a HIGH to
LOW transition of SDA when SCL is HIGH. The NM24C65Uxxx
continuously monitors the SDA and SCL lines for the start condition and
will not respond to any command until this condition has been met.
STOP CONDITION
All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the NM24C65Uxxx to place the device
in the standby power mode.
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NM24C65U Rev. B.1
www.fairchildsemi.com
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