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MT5C2565C-70L/883C

Description
Standard SRAM, 64KX4, 70ns, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28
Categorystorage    storage   
File Size143KB,11 Pages
ManufacturerMicross
Websitehttps://www.micross.com
Download Datasheet Parametric View All

MT5C2565C-70L/883C Overview

Standard SRAM, 64KX4, 70ns, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28

MT5C2565C-70L/883C Parametric

Parameter NameAttribute value
MakerMicross
Parts packaging codeDIP
package instruction0.300 INCH, CERAMIC, DIP-28
Contacts28
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
Maximum access time70 ns
JESD-30 codeR-CDIP-T28
memory density262144 bit
Memory IC TypeSTANDARD SRAM
memory width4
Number of functions1
Number of terminals28
word count65536 words
character code64000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize64KX4
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Filter levelMIL-STD-883
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width7.62 mm
SRAM
Austin Semiconductor, Inc.
64K x 4 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-89524
• MIL-STD-883
MT5C2565
PIN ASSIGNMENT
(Top View)
FEATURES
High Speed: 12, 15, 20, 25, 35, and 45ns
Battery Backup: 2V data retention
Low power standby
High-performance, low-power, CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\
• All inputs and outputs are TTL compatible
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
CE\
OE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
A15
A14
A13
A12
A11
A10
NC
NC
DQ4
DQ3
DQ2
DQ1
WE\
A1
A0
NC
Vcc
NC
3 2 1 28 27
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
1 0
A9
1 1
CE\
1 2
13 14 15 16 17
DQ1
WE\
NC
Vss
OE\
26
25
24
23
22
21
20
19
18
28-Pin DIP (C)
(300 MIL)
28-Pin LCC (EC)
A15
A14
A13
A12
A11
A10
DQ4
DQ3
DQ2
OPTIONS
• Timing
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
• Package(s)
Ceramic DIP (300 mil)
Ceramic LCC
MARKING
-15
-20
-25
-35
-45
-55*
-70*
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs
high-speed, low-power CMOS designs using a four-transistor
memory cell. Austin Semiconductor SRAMs are fabricated
using double-layer metal, double-layer polysilicon
technology.
For flexibility in high-speed memory applications,
Austin Semiconductor offers chip enable (CE\) and output
enable (OE\) capability. These enhancements can place the
outputs in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write enable
(WE\) and CE\ inputs are both LOW. Reading is accomplished
when WE\ remains HIGH and CE\ and OE\ go LOW. The
device offers a reduced power standby mode when disabled.
This allows system designs to achieve low standby power
requirements.
The “L” version provides an approximate 50 percent
reduction in CMOS standby current (I
SBC2
) over the standard
version.
All devices operate from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
C
EC
No.108
No. 204
• Operating Temperature Ranges
Industrial (-40
o
C to +85
o
C)
IT
o
o
Military (-55 C to +125 C)
XT
• 2V data retention/low power
L
*Electrical characteristics identical to those provided for the 45ns
access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C2565
Rev. 1.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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