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MT48LC2M32B2TG-8

Description
Synchronous DRAM, 2MX32, 6ns, CMOS, PDSO86, 0.400 INCH, PLASTIC, TSOP-86
Categorystorage    storage   
File Size2MB,51 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric View All

MT48LC2M32B2TG-8 Overview

Synchronous DRAM, 2MX32, 6ns, CMOS, PDSO86, 0.400 INCH, PLASTIC, TSOP-86

MT48LC2M32B2TG-8 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerMicron Technology
Parts packaging codeTSOP
package instruction0.400 INCH, PLASTIC, TSOP-86
Contacts86
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time6 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)125 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PDSO-G86
JESD-609 codee0
length22.22 mm
memory density67108864 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width32
Number of functions1
Number of ports1
Number of terminals86
word count2097152 words
character code2000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize2MX32
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Encapsulate equivalent codeTSSOP86,.46,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)235
power supply3.3 V
Certification statusNot Qualified
refresh cycle4096
Maximum seat height1.2 mm
self refreshYES
Continuous burst length1,2,4,8,FP
Maximum standby current0.002 A
Maximum slew rate0.225 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width10.16 mm
64Mb: x32
SDRAM
SYNCHRONOUS
DRAM
FEATURES
• PC100 functionality
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh (15.6µs/row)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency of 1, 2, and 3
MT48LC2M32B2 - 512K x 32 x 4 banks
For the latest data sheet, please refer to the Micron
Web site:
www.micron.com/mti/msp/html/datasheet.html
PIN ASSIGNMENT (TOP VIEW)
86-PIN TSOP
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
DD
DQM0
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10
A0
A1
A2
DQM2
V
DD
NC
DQ16
V
SS
Q
DQ17
DQ18
V
DD
Q
DQ19
DQ20
V
SS
Q
DQ21
DQ22
V
DD
Q
DQ23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
DQM1
NC
NC
CK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
DD
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
DD
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
OPTIONS
• Configuration
2 Meg x 32 (512K x 32 x 4 banks)
• Plastic Package - OCPL
1
86-pin TSOP (400 mil)
• Timing (Cycle Time)
6ns (166 MHz)
7ns (143 MHz)
8ns (125 MHz)
• Operating Temperature Range
Commercial (0° to +70°C)
Extended (-40°C to +85°C)
NOTE:
1. Off-center parting line
2. Available on the -7
Part Number Example:
MARKING
2M32B2
TG
-6
-7
-8
None
IT
2
MT48LC2M32B2TG-7
64Mb (x32) SDRAM PART NUMBER
PART NUMBER
MT48LC2M32B2TG
ARCHITECTURE
2 Meg x 32
Note:
The # symbol indicates signal is active LOW.
KEY TIMING PARAMETERS
SPEED
GRADE
-6
-7
-8
CLOCK
ACCESS TIME
FREQUENCY
CL = 3*
166 MHz
143 MHz
125 MHz
5.5ns
5.5ns
6ns
SETUP
TIME
1.5ns
2ns
2ns
HOLD
TIME
1ns
1ns
1ns
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
2 Meg x 32
512K x 32 x 4 banks
4K
2K (A0-A10)
4 (BA0, BA1)
256 (A0-A7)
*CL = CAS (READ) latency
64Mb: x32 SDRAM
64MSDRAMx32_4_00.p65 – Rev. 4/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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