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TSPC106AVG83CE

Description
PCI Bus Controller, CMOS, CBGA303, 21 X 25 MM, 3.16 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-303
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size570KB,40 Pages
Manufacturere2v technologies
Download Datasheet Parametric View All

TSPC106AVG83CE Overview

PCI Bus Controller, CMOS, CBGA303, 21 X 25 MM, 3.16 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-303

TSPC106AVG83CE Parametric

Parameter NameAttribute value
Makere2v technologies
Parts packaging codeBGA
package instructionBGA,
Contacts303
Reach Compliance Codecompliant
ECCN code3A001.A.3
Address bus width32
Bus compatibility60X; POWERPC 601; POWERPC 603; POWERPC 604
maximum clock frequency83.3 MHz
External data bus width64
JESD-30 codeR-CBGA-B303
length25 mm
Number of terminals303
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeBGA
Package shapeRECTANGULAR
Package formGRID ARRAY
Certification statusNot Qualified
Maximum seat height3.16 mm
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Terminal formBALL
Terminal pitch1.27 mm
Terminal locationBOTTOM
width21 mm
uPs/uCs/peripheral integrated circuit typeBUS CONTROLLER, PCI
Features
Processor Bus Frequency Up to 66 MHz and 83.3 MHz
64-bit Data Bus and 32-bit Address Bus
L2 Cache Control for 256-Kbyte, 512-Kbyte, 1-Mbyte Sizes
Provides Support for Either Asynchronous SRAM, Burst SRAM
or Pipelined Burst SRAM
Compliant with PCI Specification, Revision 2.1
PCI Interface Operates at 20 to 33 MHz, 3.3V/5.0V-compatible
IEEE 1149.1-compliant, JTAG Boundary-scan Interface
P
D
Max = 1.7 Watts (66 MHz), Full Operating Conditions
Nap, Doze and Sleep Modes Reduce Power Consumption
Fully Compliant with MIL-STD-883 Class Q or According to Atmel Standards
Upscreenings Based on Atmel Standards
Full Military Temperature Range (-55°C
T
C
+125°C)
– Industrial Temperature Range (-40°C
T
C
+110°C)
V
CC
= 3.3V ± 5%
Available in a 303-ball CBGA or a 303-ball CBGA with Solder Column Interposer (SCI)
(CI-CGA) Package
PCI Bridge/
Memory
Controller
TSPC106
Description
The TSPC106 provides an integrated, high-bandwidth, high-performance, TTL-com-
patible interface between a 60x processor, a secondary (L2) cache or up to a total of
four additional 60x processors, the PCI bus and main memory.
PCI support allows system designers to rapidly design systems using peripherals
already designed for PCI.
The TSPC106 uses an advanced 3.3V CMOS-process technology and maintains full
interface compatibility with TTL devices.
The TSPC106 integrates system testability and debugging features via JTAG bound-
ary-scan capability.
G suffix
CBGA 303
Ceramic Ball Grid Array
GS suffix
CI±CGA 303
Ceramic Ball Grid Array
with Solder Column Interposer (SCI)
Rev. 2102B–HIREL–02/02
1
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