5. In the event of more than one fault/warning condition occurring, the higher priority condition will take precedence. E.g. ‘Excessive coil current’ and
‘Out of regulation’ occurring together will produce an output of 0.9V on the STATUS pin. The voltage levels on the STATUS output assume the
Internal regulator to be in regulation and V
ADJ
<=V
REF
. A reduction of the voltage on the STATUS pin will occur when the voltage on V
IN
is near the
minimum value of 6V.
6. Flag is asserted if V
SHP
<2.5V or V
SHP
>3.5V
7. GATE is switched to the supply voltage V
AUX
for low values of V
AUX
(i.e. between 6V and approximately 12V). For V
AUX
>12V, GATE is clamped
internally to prevent it exceeding 15V.
8. GATE is switched to PGND by an NMOS transistor
9. If t
ON
exceeds t
STALL
, the device will force GATE low to turn off the external switch and then initiate a restart cycle. During this phase, ADJ is
grounded internally and the SHP pin is switched to its nominal operating voltage, before operation is allowed to resume. Restart cycles will be
repeated automatically until the operating conditions are such that normal operation can be sustained. If t
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