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DATA SHEET
DARLINGTON POWER TRANSISTOR
2SD2163
NPN SILICON EPITAXIAL TRANSISTOR (DARLINGTON CONNECTION)
FOR LOW-FREQUENCY POWER AMPLIFIERS AND
LOW-SPEED HIGH-CURRENT SWITCHING
PACKAGE DRAWING (UNIT: mm)
The 2SD2163 is a mold power transistor developed for low-
speed high-current switching. This transistor is ideal for direct
driving from the IC output of devices such as pulse motor drivers
and relay drivers of PC terminals.
FEATURES
• Mold package that does not require an insulating board or
insulation bushing
• High DC current gain due to Darlington connection
h
FE
= 1,000 MIN. (@I
C
= 10 A)
• Low collector saturation voltage:
V
CE(sat)
= 1.5 V MAX. (@I
C
= 10 A)
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
°
Parameter
Collector to base voltage
Collector to emitter voltage
Emitter to base voltage
Collector current (DC)
Collector current (pulse)
Base current (DC)
Total power dissipation
Total power dissipation
Junction temperature
Storage temperature
Symbol
V
CBO
V
CEO
V
EBO
I
C(DC)
I
C(pulse)
*
I
B(DC)
P
T
(Tc = 25°C)
P
T
(Ta = 25°C)
T
j
T
stg
Ratings
150
100
8.0
±10
±20
1.0
30
2.0
150
−55
to +150
Unit
V
V
V
A
A
A
W
W
°C
°C
Electrode Connection
*
PW
≤
10 ms, duty cycle
≤
50%
ELECTRICAL CHARACTERISTICS (Ta = 25°C)
°
Parameter
Collector cutoff current
DC current gain
Collector saturation voltage
Base saturation voltage
Turn-on time
Storage time
Fall time
Symbol
I
CBO
h
FE
**
V
CE(sat)
**
V
BE(sat)
**
t
on
t
stg
t
f
Conditions
V
CB
= 100 V, I
E
= 0
V
CE
= 2.0 V, I
C
= 10 A
I
C
= 10 A, I
B
= 25 mA
I
C
= 10 A, I
B
= 25 mA
I
C
= 10 A, I
B1
=
−I
B2
= 25 mA
R
L
= 5.0
Ω,
V
CC
≅
50 V
Refer to the test circuit.
1,000
6,000
1.1
1.8
1.0
5.0
2.0
MIN.
TYP.
MAX.
10
30,000
1.5
2.0
Unit
µ
A
V
V
µ
s
µ
s
µ
s
** Pulse test PW
≤
350
µ
s, duty cycle
≤
2%
h
FE
CLASSIFICATION
Marking
h
FE
M
1,000 to 3,000
L
2,000 to 5,000
K
4,000 to 10,000
J
8,000 to 30,000
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. D16139EJ1V0DS00 (1st edition)
Date Published April 2002 N CP(K)
Printed in Japan
©
2002
1998
Embedded System
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