1.6 V, Micropower 12-/10-/8-Bit ADCs
AD7466/AD7467/AD7468
FEATURES
Specified for V
DD
of 1.6 V to 3.6 V
Low power:
0.62 mW typical at 100 kSPS with 3 V supplies
0.48 mW typical at 50 kSPS with 3.6 V supplies
0.12 mW typical at 100 kSPS with 1.6 V supplies
Fast throughput rate: 200 kSPS
Wide input bandwidth:
71 dB SNR at 30 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI/QSPI™/MICROWIRE™/DSP compatible
Automatic power-down
Power-down mode: 8 nA typical
6-lead SOT-23 package
8-lead MSOP package
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
IN
T/H
12-/10-/8-BIT
SUCCESSIVE
APPROXIMATION
ADC
SCLK
CONTROL
LOGIC
SDATA
CS
GND
Figure 1.
APPLICATIONS
Battery-powered systems
Medical instruments
Remote data acquisition
Isolated data acquisition
GENERAL DESCRIPTION
The AD7466/AD7467/AD7468
1
are 12-/10-/8-bit, high speed,
low power, successive approximation analog-to-digital
converters (ADCs), respectively. The parts operate from a single
1.6 V to 3.6 V power supply and feature throughput rates up to
200 kSPS with low power dissipation. The parts contain a low
noise, wide bandwidth track-and-hold amplifier, which can
handle input frequencies in excess of 3 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS, and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.
The reference for the part is taken internally from V
DD
. This
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the part is 0 V to V
DD
. The conversion
rate is determined by the SCLK.
1
PRODUCT HIGHLIGHTS
1.
2.
3.
Specified for supply voltages of 1.6 V to 3.6 V.
12-, 10-, and 8-bit ADCs in SOT-23 and MSOP packages.
High throughput rate with low power consumption.
Power consumption in normal mode of operation at
100 kSPS and 3 V is 0.9 mW maximum.
Flexible power/serial clock speed management.
The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced through
increases in the serial clock speed. Automatic power-down
after conversion allows the average power consumption to
be reduced when in power-down. Current consumption is
0.1 μA maximum and 8 nA typically when in power-down.
Reference derived from the power supply.
No pipeline delay.
The part features a standard successive approximation
ADC with accurate control of conversions via a CS input.
4.
5.
6.
7.
Protected by U.S. Patent No. 6,681,332.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.
02643-001
AD7466/AD7467/AD7468
AD7466/AD7467/AD7468
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD7466 .......................................................................................... 3
AD7467 .......................................................................................... 5
AD7468 .......................................................................................... 7
Timing Specifications .................................................................. 9
Timing Examples........................................................................ 10
Absolute Maximum Ratings.......................................................... 11
ESD Caution................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 13
Dynamic Performance Curves ................................................. 13
DC Accuracy Curves ................................................................. 13
Power Requirement Curves ...................................................... 13
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
Circuit Information.................................................................... 17
Converter Operation.................................................................. 17
ADC Transfer Function............................................................. 17
Typical Connection Diagram ................................................... 17
Analog Input ............................................................................... 18
Digital Inputs .............................................................................. 18
Normal Mode.............................................................................. 19
Power Consumption .................................................................. 20
Serial Interface ................................................................................ 22
Microprocessor Interfacing....................................................... 23
Application Hints ........................................................................... 25
Grounding and Layout .............................................................. 25
Evaluating the Performance of the AD7466 and AD7467.... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 27
REVISION HISTORY
5/07—Rev. B to Rev. C
Deleted Figure 3.............................................................................. 10
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 27
4/05—Rev. A to Rev. B
Moved Terminology Section......................................................... 16
Changes to Ordering Guide .......................................................... 27
11/04—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to General Description .................................................... 1
Added Patent Number ..................................................................... 1
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 27
5/03—Revision 0: Initial Version
Rev. C | Page 2 of 28
AD7466/AD7467/AD7468
SPECIFICATIONS
AD7466
V
DD
= 1.6 V to 3.6 V, f
SCLK
= 3.4 MHz, f
SAMPLE
= 100 kSPS, unless otherwise noted. T
A
= T
MIN
to T
MAX
, unless otherwise noted.
The temperature range for the B version is −40°C to +85°C.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion (SINAD)
B Version
69
70
70
70
71
71
70.5
−83
−85
Unit
dB min
dB min
dB typ
dB min
dB typ
dB min
dB typ
dB typ
dB typ
Test Conditions/Comments
f
IN
= 30 kHz sine wave
1.8 V ≤ V
DD
≤ 2 V; see the Terminology section
2.5 V ≤ V
DD
≤ 3.6 V
V
DD
= 1.6 V
1.8 V ≤ V
DD
≤ 2 V; see the Terminology section
1.8 V ≤ V
DD
≤ 2 V
2.5 V ≤ V
DD
≤ 3.6 V
V
DD
= 1.6 V
See the Terminology section
See the Terminology section
fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology
section
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
−84
−86
10
40
3.2
1.9
750
450
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
kHz typ
kHz typ
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Total Unadjusted Error (TUE)
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
12
±1.5
−0.9/+1.5
±1
±1
±2
0 to V
DD
±1
20
0.7 × V
DD
2
0.2 × V
DD
0.3 × V
DD
0.8
±1
±1
10
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
V
μA max
pF typ
V min
V min
V max
V max
V max
μA max
μA typ
pF max
@ 3 dB, 2.5 V ≤ V
DD
≤ 3.6 V
@ 3 dB, 1.6 V ≤ V
DD
≤ 2.2 V
@ 0.1 dB, 2.5 V ≤ V
DD
≤ 3.6 V
@ 0.1 dB, 1.6 V ≤ V
DD
≤ 2.2 V
Maximum specifications apply as typical figures when
V
DD
= 1.6 V
See the Terminology section
Guaranteed no missed codes to 12 bits; see the
Terminology section
See the Terminology section
See the Terminology section
See the Terminology section
Input Current, I
IN
, SCLK Pin
Input Current, I
IN
, CS Pin
Input Capacitance, C
IN
1.6 V ≤ V
DD
< 2.7 V
2.7 V ≤ V
DD
≤ 3.6 V
1.6 V ≤ V
DD
< 1.8 V
1.8 V ≤ V
DD
< 2.7 V
2.7 V ≤ V
DD
≤ 3.6 V
Typically 20 nA, V
IN
= 0 V or V
DD
Sample tested at 25°C to ensure compliance
Rev. C | Page 3 of 28
AD7466/AD7467/AD7468
Parameter
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
CONVERSION RATE
Conversion Time
Throughput Rate
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode (Operational)
B Version
V
DD
− 0.2
0.2
±1
10
Straight (natural)
binary
4.70
200
1.6/3.6
300
110
20
240
80
16
165
50
10
0.1
0.9
0.6
0.3
0.3
Unit
V min
V max
μA max
pF max
Test Conditions/Comments
I
SOURCE
= 200 μA, V
DD
= 1.6 V to 3.6 V
I
SINK
= 200 μA
μs max
kSPS max
V min/max
μA max
μA typ
μA typ
μA max
μA typ
μA typ
μA max
μA typ
μA typ
μA max
mW max
mW max
mW max
μW max
16 SCLK cycles with SCLK at 3.4 MHz
See the Serial Interface section
Power-Down Mode
Power Dissipation
Normal Mode (Operational)
Power-Down Mode
Digital inputs = 0 V or V
DD
V
DD
= 3 V, f
SAMPLE
= 100 kSPS
V
DD
= 3 V, f
SAMPLE
= 50 kSPS
V
DD
= 3 V, f
SAMPLE
= 10 kSPS
V
DD
= 2.5 V, f
SAMPLE
= 100 kSPS
V
DD
= 2.5 V, f
SAMPLE
= 50 kSPS
V
DD
= 2.5 V, f
SAMPLE
= 10 kSPS
V
DD
= 1.8 V, f
SAMPLE
= 100 kSPS
V
DD
= 1.8 V, f
SAMPLE
= 50 kSPS
V
DD
= 1.8 V, f
SAMPLE
= 10 kSPS
SCLK on or off, typically 8 nA
See the Power Consumption section
V
DD
= 3 V, f
SAMPLE
= 100 kSPS
V
DD
= 2.5 V, f
SAMPLE
= 100 kSPS
V
DD
= 1.8 V, f
SAMPLE
= 100 kSPS
V
DD
= 3 V
Rev. C | Page 4 of 28
AD7466/AD7467/AD7468
AD7467
V
DD
= 1.6 V to 3.6 V, f
SCLK
= 3.4 MHz, f
SAMPLE
= 100 kSPS, unless otherwise noted. T
A
= T
MIN
to T
MAX
, unless otherwise noted.
The temperature range for the B version is −40°C to +85°C.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion (SINAD)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
B Version
Unit
Test Conditions/Comments
Maximum/minimum specifications apply as typical figures
when V
DD
= 1.6 V, f
IN
= 30 kHz sine wave
See the Terminology section
See the Terminology section
See the Terminology section
fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology section
61
−72
−74
−83
−83
10
40
3.2
1.9
750
450
dB min
dB max
dB max
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
kHz typ
kHz typ
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Total Unadjusted Error (TUE)
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
10
±0.5
±0.5
±0.2
±0.2
±1
0 to V
DD
±1
20
0.7 × V
DD
2
0.2 × V
DD
0.3 × V
DD
0.8
±1
±1
10
V
DD
− 0.2
0.2
±1
10
Straight (natural)
binary
3.52
275
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
V
μA max
pF typ
V min
V min
V max
V max
V max
μA max
μA typ
pF max
V min
V max
μA max
pF max
@ 3 dB, 2.5 V ≤ V
DD
≤ 3.6 V
@ 3 dB, 1.6 V ≤ V
DD
≤ 2.2 V
@ 0.1 dB, 2.5 V ≤ V
DD
≤ 3.6 V
@ 0.1 dB, 1.6 V ≤ V
DD
≤ 2.2 V
Maximum specifications apply as typical figures when
V
DD
= 1.6 V
See the Terminology section
Guaranteed no missed codes to 10 bits; see the
Terminology section
See the Terminology section
See the Terminology section
See the Terminology section
Input Current, I
IN
, SCLK Pin
Input Current, I
IN
, CS Pin
Input Capacitance, C
IN
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
CONVERSION RATE
Conversion Time
Throughput Rate
1.6 V ≤ V
DD
< 2.7 V
2.7 V ≤ V
DD
≤ 3.6 V
1.6 V ≤ V
DD
< 1.8 V
1.8 V ≤V
DD
< 2.7 V
2.7 V ≤ V
DD
≤ 3.6 V
Typically 20 nA, V
IN
= 0 V or V
DD
Sample tested at 25°C to ensure compliance
I
SOURCE
= 200 μA, V
DD
= 1.6 V to 3.6 V
I
SINK
= 200 μA
Sample tested at 25°C to ensure compliance
μs max
kSPS max
12 SCLK cycles with SCLK at 3.4 MHz
See the Serial Interface section
Rev. C | Page 5 of 28
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