General Features
•
Single-package Fully-integrated Atmel
®
AVR
®
8-bit Microcontroller with LIN
•
•
•
•
•
•
Transceiver, 5V Regulator and Watchdog
Very Low Current Consumption in Sleep Mode
8 Kbytes/16 Kbytes Flash Memory for Application Program (ATA6612/ATA6613)
Supply Voltage Up to 40V
Operating Voltage: 5V to 27V
Temperature Range: T
case
–40°C to +125°C
QFN48, 7 mm
×
7 mm Package
1. Description
ATA6612/ATA6613 is a System-in-Package (SiP) product, which is particularly suited
for complete LIN-bus slave-node applications. It supports highly integrated solutions
for in-vehicle LIN networks. The first chip is the LIN-system-basis-chip (LIN-SBC)
ATA6624, which has an integrated LIN transceiver, a 5V regulator and a window
watchdog. The second chip is an automotive microcontroller from Atmel’s series of
Atmel AVR 8-bit microcontroller with advanced RISC architecture.
The ATA6612 consists of the LIN-SBC ATA6624 and the ATmega88 with 8 Kbytes
flash. The ATA6613 consists of the LIN-SBC ATA6624 and the ATmega168 with
16 Kbytes flash. All pins of the LIN System Basis Chip as well as all pins of the Atmel
AVR microcontroller are bonded out to provide customers the same flexibility for their
applications as they have when using discrete parts.
In section 2 you will find the pin configuration for the complete SiP. In sections 3 to 5
the LIN SBC is described, and in sections 6 to 7 the Atmel AVR is described in detail.
Figure 1-1.
Application Diagram
LIN Bus
Microcontroller
with LIN
Transceiver,
5V Regulator
and Watchdog
ATA6612
ATA6613
ATA6612/ATA6613
MCU
ATmega88
or
ATmega168
LIN-SBC
ATA6624
9111G–AUTO–05/10
2. Pin Configuration
Figure 2-1.
Pinning QFN48, 7 mm
×
7 mm
PB4
PB3
PB2
PB1
PB0
PD7
PD6
PD5
PB7
PB6
MCUVDD2
GND2
PB5
MCUAVDD
ADC6
AREF
GND4
ADC7
PC0
PC1
PC2
PC3
PC4
PC5
48 47 46 45 44 43 42 41 40 39 38 37
36
1
35
2
34
3
33
4
32
5
31
6
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
PC6
PD0
PD1
PD2
RXD
INH
TXD
NRES
WD_OSC
TM
MODE
KL_15
MCUVDD1
GND1
PD4
PD3
LIN
GND
WAKE
NTRIG
EN
VS
VCC
PVCC
Table 2-1.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
(1)
Pin Description
Symbol
PB5
MCUAVDD
ADC6
AREF
GND4
ADC7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PD0
PD1
PD2
RXD
INH
TXD
Function
Port B 5 I/O line (SCK / PCINT5)
Microcontroller ADC-unit supply voltage
ADC input channel 6
Analog reference voltage input
Ground
ADC input channel 7
Port C 0 I/O line (ADC0/PCINT8)
Port C 1 I/O line (ADC1/PCINT9)
Port C 2 I/O line (ADC2/PCINT10)
Port C 3 I/O line (ADC3/PCINT11)
Port C 4 I/O line (ADC4/SDA/PCINT12)
Port C 5 I/O line (ADC5/SCL/PCINT13)
Port C 6 I/O line (RESET/PCINT14)
Port D 0 I/O line (RXD/PCINT16)
Port D 1 I/O line (TXD/PCINT17)
Port D 2 I/O line (INT0/PCINT18)
Receive data output
High side switch output for controlling an external voltage regulator
Transmit data input / active low output after a local wake up request
18
(1)
19
(1)
Note:
1. This identifies the pins of the LIN SBC ATA6624
2
ATA6612/ATA6613
9111G–AUTO–05/10
ATA6612/ATA6613
Table 2-1.
Pin
20
(1)
21
(1)
22
(1)
23
(1)
24
(1)
25
(1)
26
(1)
27
(1)
28
(1)
29
(1)
30
(1)
31
(1)
32
(1)
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Backside
Note:
Pin Description (Continued)
Symbol
NRES
WD_OSC
TM
MODE
KL_15
PVCC
VCC
VS
EN
NTRIG
WAKE
GND
LIN
PD3
PD4
GND1
MCUVDD1
GND2
MCUVDD2
PB6
PB7
PD5
PD6
PD7
PB0
PB1
PB2
PB3
PB4
Function
Watchdog and undervoltage reset output (open drain)
External resistor for adjustable watchdog timing
Tie to Ground – for factory use only
Connect to GND for normal watchdog operation or connect to VCC for debug mode
Ignition detection (edge sensitive)
Voltage regulator sense input
Voltage regulator output
Battery connection
LIN-transceiver enable input
Watchdog trigger input (negative edge)
System-basis-chip external wake-up input
Analog system GND
LIN-bus input/output
Port D 3 I/O line (INT1 OC2B/PCINT19)
Port D 4 I/O line (T0/XCK/PCINT20)
Ground
Microcontroller supply voltage
Ground
Microcontroller supply voltage
Port B 6 I/O line (TOSC1/XTAL1/PCINT6)
Port B 7 I/O line (TOSC2/XTAL2/PCINT7)
Port D 5 I/O line (T1/OC0B/PCINT21)
Port D 6 I/O line (AIN0/OC0A PCINT22)
Port D 7 I/O line (AIN1/PCINT23)
Port B 0 I/O line (ICP1/CLKO/PCINT0)
Port B 1 I/O line (OC1A/PCINT1)
Port B 2 I/O line (OC1B/SS/PCINT2)
Port B 3 I/O line (MOSI/OC2A/PCINT3)
Port B 4 I/O line (MISO/PCINT4)
Heat slug is connected to GND
1. This identifies the pins of the LIN SBC ATA6624
3
9111G–AUTO–05/10
Table 2-2.
Maximum Ratings of the SiP
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
HBM ESD
ANSI/ESD-STM5.1
JESD22-A114
AEC-Q100 (002)
CDM ESD STM 5.3.1
Storage temperature
Operating temperature
(1)
Thermal resistance junction to heat slug
Thermal resistance junctiion to ambient
Thermal shutdown of VCC regulator
Thermal shutdown of LIN output
Thermal shutdown hysteresis
Note:
T
s
T
case
R
thjc
R
thja
150
150
Symbol
Min.
Typ.
Max.
Unit
±2
KV
±750
–55
–40
6
30
165
165
10
170
170
+150
+125
V
°C
°C
K/W
K/W
°C
°C
°C
1. T
case
means the temperature of the heat slug (backside). It is mandatory that this backside temperature is
≤
125°C in the
application.
4
ATA6612/ATA6613
9111G–AUTO–05/10
ATA6612/ATA6613
3. LIN System-basis-chip Block
3.1
Features
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Master and Slave Operation Possible
Supply Voltage up to 40V
Operating voltage V
S
= 5V to 27V
Typically 10 µA Supply Current During Sleep Mode
Typically 57 µA Supply Current in Silent Mode
Linear Low-drop Voltage Regulator:
Normal, Fail-safe, and Silent Mode
V
CC
= 5.0V ±2%
In Sleep Mode V
CC
is Switched Off
VCC- Undervoltage Detection (4 ms Reset Time) and Watchdog Reset Logical Combined at Open
Drain Output NRES
Negative Trigger Input for Watchdog
Boosting the Voltage Regulator Possible with an External NPN Transistor
LIN Physical Layer According to LIN 2.0, 2.1 Specification and SAEJ2602-2
Wake-up Capability via LIN-bus, Wake Pin, or Kl_15 Pin
INH Output to Control an External Voltage Regulator or to Switch off the Master Pull Up Resistor
TXD Time-out Timer
Bus Pin is Overtemperature and Short Circuit Protected versus GND and Battery
Adjustable Watchdog Time via External Resistor
Advanced EMC and ESD Performance
ESD HBM 8 kV at Pins LIN and VS According to STM5.1
3.2
Description
The LIN-SBC is a fully integrated LIN transceiver, which complies with the LIN 2.1 and
SAEJ2602-2 specifications. It has a low-drop voltage regulator for 5V/50 mA output and a win-
dow watchdog.
The LIN-SBC are designed to handle the low-speed data communication in vehicles, e.g., in
convenience electronics. Improved slope control at the LIN-driver ensures secure data commu-
nication up to 20 kBaud. Sleep Mode and Silent Mode guarantee very low current consumption.
5
9111G–AUTO–05/10
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