Features
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Supply Voltage up to 40V
R
DSon
Typically 0.8Ω at 25°C, Maximum 1.8Ω at 200°C
Up to 1.0A Output Current
Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers
Capable to Switch all Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors
and Inductors
No Shoot-through Current
Outputs Short-circuit Protected
Overtemperature Protection for Each Switch and Overtemperature Prewarning
Undervoltage Protection
Various Diagnostic Functions Such as Shorted Output, Open-load, Overtemperature
and Power-supply Fail Detection
Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency
QFN18 Package
1. Description
The ATA6827 is a fully protected driver IC specially designed for high temperature
applications. In mechatronic solutions, for example turbo charger or exhaust gas recir-
culation systems, many flaps have to be controlled by DC motor driver ICs which are
located very close to the hot engine or actuator where ambient temperatures up to
150°C are usual. Due to the advantages of SOI technology junction temperatures up
to 200°C are allowed. This enables new cost effective board design possibilities to
achieve complex mechatronic solutions.
The ATA6827 is a fully protected Triple Half-Bridge to control up to 3 different loads by
a microcontroller in automotive and industrial applications. Each of the 3 high-side and
3 low-side drivers is capable to drive currents up to 1.0A. The drivers are internally
connected to form 3 half-bridges and can be controlled separately from a standard
serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors
and inductors can be combined. The IC design especially supports the application of
H-bridges to drive DC motors.
Protection is guaranteed regarding short-circuit conditions, overtemperature and
undervoltage. Various diagnostic functions and a very low quiescent current in
standby mode opens a wide range of applications. Automotive qualification gives
added value and enhanced quality for exacting requirements of automotive
applications.
High
Temperature
Triple
Half-bridge
Driver with
Serial Input
Control
ATA6827
4912E–AUTO–02/10
Figure 1-1.
Block Diagram
n.
u.
n.
u.
O
S
C
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
10
VS
11
Input register
Ouput register
Serial interface
Charge
pump
L
S
1
T
P
VS
DI
4
CLK
5
P
S
F
O
P
L
S
C
D
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
n. H
u. S
3
L
S
3
H
S
2
L
S
2
H
S
1
CS
3
INH
8
DO
7
Control
logic
Power on
reset
14
GND
17
Fault
detector
Fault
detector
Fault
detector
Fault
detector
Fault
detector
Fault
detector
UV
protection
9
VCC
GND
Thermal
protection
18
GND
6
1
OUT3S
2
OUT3F
13
OUT2S
12
OUT2F
16
OUT1S
15
OUT1F
GND
2
ATA6827
4912E–AUTO–02/10
ATA6827
2. Pin Configuration
Figure 2-1.
Pinning QFN18
PGND3
PGND1
OUT1S
OUT1F
PGND2
OUT2S
OUT3S
OUT3F
CS
DI
CLK
GND
1
2
3
4
5
6
18 17 16 15 14 13
12
11
10
9
8
7
OUT2F
VS
VS
VCC
INH
DO
Table 2-1.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Pin Description
Symbol
OUT3S
OUT3F
CS
DI
CLK
GND
DO
INH
VCC
VS
VS
OUT2F
OUT2S
PGND2
OUT1F
OUT1S
PGND1
PGND3
PGND1
PGND3
Function
Used only for final testing, to be connected to OUT3F
Half-bridge output 3
Chip select input; 5-V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled
Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control
device; DI expects a 16-bit control word with LSB being transferred first
Serial clock input; 5-V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (f
max
= 2 MHz)
Ground; reference potential
Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit
status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless
device is selected by CS = low, therefore, several ICs can operate on one data output line only.
Inhibit input; 5-V logic input with internal pull down; low = standby, high = normal operation
Logic supply voltage (5 V)
Power supply for output stages OUT1, OUT2 and OUT3, internal supply
Power supply for output stages OUT1, OUT2 and OUT3, internal supply
Half-bridge output 2
Used only for final testing, to be connected to OUT2F
Power Ground OUT2
Half-bridge output 1
Used only for final testing, to be connected to OUT13F
Power Ground OUT1 and OUT3
Power Ground OUT1 and OUT3
3
4912E–AUTO–02/10
3. Functional Description
3.1
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans-
ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS
is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output
data will change their state with the rising edge of CLK and stay stable until the next rising edge
of CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3-1.
CS
Data Transfer
DI
SRR
0
LS1
1
HS1
2
LS2
3
HS2
4
LS3
5
HS3
6
n. u.
7
n. u.
8
n. u.
9
n. u.
10
n. u.
11
n. u.
12
OCS
13
n. u.
14
n. u.
15
CLK
DO
TP
S1L
S1H
S2L
S2H
S3L
S3H
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
SCD
OPL
PSF
Table 3-1.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Input Data Protocol
Input Register
SRR
LS1
HS1
LS2
HS2
LS3
HS3
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
OCS
n. u.
n. u.
Function
Status register reset (high = reset; the bits PSF, OPL and SCD in the
output data register are set to low)
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
See LS1
See HS1
See LS1
See HS1
Not used
Not used
Not used
Not used
Not used
Not used
Overcurrent shutdown (high = overcurrent shutdown is active)
Not used
Not used
4
ATA6827
4912E–AUTO–02/10
ATA6827
Table 3-2.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Output Data Protocol
Output (Status)
Register
TP
Status LS1
Status HS1
Status LS2
Status HS2
Status LS3
Status HS3
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
SCD
Function
Temperature prewarning: high = warning
High = output is on, low = output is off; not affected by SRR
High = output is on, low = output is off; not affected by SRR
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Not used
Not used
Not used
Not used
Not used
Not used
Short circuit detected: set high when at least one high-side or low-side
switch is switched off by a short-circuit condition. Bits 1 to 6 can be used
to detect the shorted switch.
Open load detected: set high, when at least one active high-side or
low-side switch sinks/sources a current below the open load threshold
current.
Power-supply fail: undervoltage at pin VS detected
14
15
OPL
PSF
After power-on reset, the input register has the following status:
Bit 15 Bit 14
x
x
Bit 13
(OCS)
H
Bit 12
x
Bit 11
x
Bit 10
x
Bit 9
x
Bit 8
x
Bit 7
x
Bit 6
(HS3)
L
Bit 5
(LS3)
L
Bit 4
(HS2)
L
Bit 3
(LS2)
L
Bit 2 Bit 1
(HS1) (LS1)
L
L
Bit 0
(SRR)
L
The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during
normal operation.
Bit 15 Bit 14
H
H
H
H
H
H
Bit 13
(OCS)
H
H
H
Bit 12
H
L
L
Bit 11
H
L
L
Bit 10
L
H
L
Bit 9
L
H
L
Bit 8
L
L
H
Bit 7
L
L
H
Bit 6
(HS3)
L
L
L
Bit 5
(LS3)
L
L
L
Bit 4
(HS2)
L
L
L
Bit 3
(LS2)
L
L
L
Bit 2 Bit 1
(HS1) (LS1)
L
L
L
L
L
L
Bit 0
(SRR)
L
L
L
5
4912E–AUTO–02/10
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