PT461616IHG-4 datasheet, PDF - EEWORLD Datasheet

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PT461616IHG-4: DescriptionDDR DRAM, 16MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, ROHS COMPLIANT, TSOP2-66; Categorystorage storage; File Size2MB，53 Pages; ManufacturerPointec Technology Co., Ltd.; Environmental Compliance

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PT461616IHG-4 Overview

DDR DRAM, 16MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, ROHS COMPLIANT, TSOP2-66

PT461616IHG-4 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Pointec Technology Co., Ltd.
package instruction	TSOP2,
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.7 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G66
length	22.22 mm
memory density	268435456 bit
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	66
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.4 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10.16 mm

PT461616IHG-4 Preview

PT461616IHG

4M x 4BANKS x 16BITS DDR

Table of Content-

7.1.

7.2.

GENERAL DESCRIPTION ........................................................................................4

FEATURES ................................................................................................................4

KEY PARAMETERS ..................................................................................................5

PIN CONFIGURATION ..............................................................................................6

PIN DESCRIPTION ....................................................................................................7

BLOCK DIAGRAM.....................................................................................................8

FUNCTIONAL DESCRIPTION...................................................................................9

Power Up Sequence..........................................................................................................9

Command Function.........................................................................................................10

7.2.1.

Bank Activate Command

......................................................................................... 10

7.2.2.

Bank Precharge Command

...................................................................................... 10

7.2.3.

Precharge All Command

.......................................................................................... 10

7.2.4.

Write Command

........................................................................................................ 10

7.2.5.

Write with Auto-precharge Command

.................................................................... 10

7.2.6.

Read Command

........................................................................................................ 10

7.2.7.

Read with Auto-precharge Command.....................................................................

7.2.8.

Mode Register Set Command

.................................................................................. 11

7.2.9.

Extended Mode Register Set Command

................................................................. 11

7.2.10.

No-Operation Command

.......................................................................................... 11

7.2.11.

Burst Read Stop Command

..................................................................................... 11

7.2.12.

Device Deselect Command

...................................................................................... 11

7.2.13.

Auto Refresh Command...........................................................................................

7.2.14.

Self Refresh Entry Command

.................................................................................. 12

7.2.15.

Self Refresh Exit Command.....................................................................................

7.2.16.

Data Write Enable /Disable Command

.................................................................... 12

7.3.

Read Operation................................................................................................................13

7.4.

Write Operation

...............................................................................................................13

7.5.

Precharge.........................................................................................................................13

7.6.

Burst Termination

...........................................................................................................13

7.7.

Refresh Operation

...........................................................................................................14

7.8.

Power Down Mode

..........................................................................................................14

7.9.

Input Clock Frequency Change during Precharge Power Down Mode......................14

7.10.

Mode Register Operation............................................................................................14

7.10.1.

Burst Length field (A2 to A0)

................................................................................... 15

7.10.2.

Addressing Mode Select (A3)

.................................................................................. 15

7.10.3.

CAS Latency field (A6 to A4)

................................................................................... 16

7.10.4.

DLL Reset bit (A8).....................................................................................................

7.10.5.

Mode Register /Extended Mode register change bits (BA0, BA1)

........................ 16

7.10.6.

Extended Mode Register field..................................................................................

7.10.7.

Reserved field

........................................................................................................... 17

OPERATING MODES ..............................................................................................18

-1-

PT461616IHG

8.1.

8.2.

8.3.

8.4.

Simplified Truth Table.....................................................................................................18

Function Truth Table.......................................................................................................19

Function Truth Table for CKE

........................................................................................22

SIMPLIFIED STATE DIAGRAM

.......................................................................................23

9.1.

9.2.

9.3.

9.4.

9.5.

9.6.

9.7.

ELECTRICAL CHARACTERISTICS........................................................................24

Absolute Maximum Ratings

...........................................................................................24

RECOMMENDED DC OPERATING CONDITIONS

.........................................................24

Capacitance

.....................................................................................................................25

Leakage and Oupput Buffer Characteristics

................................................................25

DC Characteristics

..........................................................................................................26

AC Characteristics and Operating Condition

...............................................................27

AC TEST CONDITIONS

...................................................................................................28

10.

SYSTEM CHARACTERISTICS FOR DDR SDRAM ................................................30

10.1.

10.2.

10.3.

10.4.

10.5.

10.6.

10.7.

10.8.

10.9.

Table 1: Input Slew Rate for DQ, DQS, and DM

........................................................30

Table 2: Input Setup & Hold Time Derating for Slew Rate.......................................30

Table 3: Input/Output Setup & Hold Time Derating for Slew Rate

..........................30

Table 4: Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate..........30

Table 5: Output Slew Rate Characteristics

...............................................................30

Table 6: Output Slew Rate Matching Ratio Characteristics

....................................30

Table 7: AC Overshoot/Undershoot Specification for Address and Control Pins

Table 8: Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins

..32

System Notes...............................................................................................................33

Command Input Timing

..............................................................................................35

Timing of the CLK Signals..........................................................................................35

Read Timing (Burst Length = 4)

.................................................................................36

Write Timing (Burst Length = 4).................................................................................37

DM, DATA MASK

.........................................................................................................38

Mode Register Set (MRS) Timing

...............................................................................39

Extend Mode Register Set (EMRS) Timing................................................................40

Auto-precharge Timing (Read Cycle, CL = 2)

...........................................................41

Auto-precharge Timing (Read cycle, CL = 2), continued.........................................42

Auto Precharge Timing (Write Cycle)

........................................................................43

Read Interrupted by Read (CL = 2, BL = 2, 4, 8)........................................................44

Burst Read Stop (BL = 8)

............................................................................................44

Read Interrupted by Write & BST (BL = 8)

................................................................45

Read Interrupted by Precharge (BL = 8)....................................................................45

Write Interrupted by Write (BL = 2, 4, 8)

....................................................................46

Write Interrupted by Read (CL = 2, BL = 8)

...............................................................46

Write Interrupted by Read (CL = 3, BL = 4)

...............................................................47

Write Interrupted by Precharge (BL = 8)

...................................................................47

2 Bank Interleave Read Operation (CL = 2, BL = 2)

..................................................48

-2-

11.

TIMING WAVEFORMS ............................................................................................35

11.1.

11.2.

11.3.

11.4.

11.5.

11.6.

11.7.

11.8.

11.9.

11.10.

11.11.

11.12.

11.13.

11.14.

11.15.

11.16.

11.17.

11.18.

11.19.

PT461616IHG

11.20.

11.21.

11.22.

11.23.

11.24.

11.25.

11.26.

2 Bank Interleave Read Operation (CL = 2, BL = 4)

..................................................48

4 Bank Interleave Read Operation (CL = 2, BL = 2)

..................................................49

4 Bank Interleave Read Operation (CL = 2, BL = 4)

..................................................49

Auto Refresh Cycle

.....................................................................................................50

Active Power Down Mode Entry and Exit Timing.....................................................50

Precharged Power Down Mode Entry and Exit Timing............................................50

Self Refresh Entry and Exit Timing............................................................................51

TSOP 66(II) - 400 mill

...................................................................................................52

12.

13.

PACKAGE SPECIFICATION ...................................................................................52

12.1.

REVISION HISTORY ...............................................................................................53

-3-

PT461616IHG

1. GENERAL DESCRIPTION

PT461616IHG is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM),

organized as 4,194,304 words x 4 banks x 16 bits. PT461616IHG delivers a data bandwidth of up to 500M

bytes per second (-4). To fully comply with the personal computer industrial standard, PT461616IHG is

sorted into the following speed grades: -4, -5 and -5I. The -4 is compliant to the DDR500/CL3 and CL4

specification. The -5/-5I is compliant to the DDR400/CL3 specification (the -5I grade which is guaranteed to

support -40

℃

~ 85

℃

All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference point

for the differential clock is when the CLK and /CLK signals cross during a transition. Write and Read data are

synchronized with the both edges of DQS (Data Strobe).

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or

sequential burst to maximize its performance. PT461616IHG is ideal for main memory in high performance

applications.

2. FEATURES

2.5V ±0.2V Power Supply for DDR400

2.4V ~ 2.7V Power Supply for DDR500

Up to 250MHz Clock Frequency

Double Data Rate architecture; two data transfers per clock cycle

Differential clock inputs (CLK and /CLK)

DQS is edge-aligned with data for Read; center-aligned with data for Write

CAS Latency: 2, 2.5, 3 and 4

Burst Length: 2, 4 and 8

Auto Refresh and Self Refresh

Precharged Power Down and Active Power Down

Write Data Mask

Write Latency = 1

7.8µS refresh interval (8K/64mS refresh)

Maximum burst refresh cycle: 8

Interface: SSTL_2

Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant

-4-

PT461616IHG

3. KEY PARAMETERS

SYMBOL

DESCRIPTION

CL = 2

CL = 2.5

tCK

Clock Cycle Time

CL = 3

CL = 4

tRAS

tRC

IDD0

IDD1

IDD4R

IDD4W

IDD5

IDD6

Active to Precharge Command Period

Active to Ref/Active Command Period

Operation Current: One Bank Active-Precharge

Operation Current: One Bank Active-Read-Precharge

Burst Operation Current

Auto Refresh Burst Current

Self-Refresh Current

MIN./MAX.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

-4

4 nS

12 nS

4 nS

12 nS

36 nS

52 nS

75 mA

90 mA

140 mA

135 mA

70 mA

2 mA

-5

7.5 nS

12 nS

6 nS

12 nS

5 nS

12 nS

40 nS

55 nS

65 mA

80 mA

120 mA

115 mA

65 mA

2 mA

-5-

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PT461616IHG-4 Related Products

	PT461616IHG-4	PT461616IHG-5
Description	DDR DRAM, 16MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, ROHS COMPLIANT, TSOP2-66	DDR DRAM, 16MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, ROHS COMPLIANT, TSOP2-66
Is it Rohs certified?	conform to	conform to
Maker	Pointec Technology Co., Ltd.	Pointec Technology Co., Ltd.
package instruction	TSOP2,	TSOP2,
Reach Compliance Code	unknown	unknown
ECCN code	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	0.7 ns	0.7 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G66	R-PDSO-G66
length	22.22 mm	22.22 mm
memory density	268435456 bit	268435456 bit
Memory IC Type	DDR DRAM	DDR DRAM
memory width	16	16
Number of functions	1	1
Number of ports	1	1
Number of terminals	66	66
word count	16777216 words	16777216 words
character code	16000000	16000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C
organize	16MX16	16MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
Maximum seat height	1.2 mm	1.2 mm
self refresh	YES	YES
Maximum supply voltage (Vsup)	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.4 V	2.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	10.16 mm	10.16 mm

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