LPC55S2x/LPC552x
32-bit Arm Cortex
®
-M33, CASPER, 256 KB SRAM; 512 KB
flash, USB HS, Flexcomm Interface, SDIO, 32-bit counter/
timers, SCTimer/PWM, PLU, 16-bit 1.0 Msamples/sec ADC,
Comparator, Temperature Sensor, AES, PUF, SHA, CRC, RNG
Rev. 1.5 — 17 October 2019
Product data sheet
1. General description
The LPC55S2x/LPC552x is an ARM Cortex-M33 based microcontroller for embedded
applications. These devices include a CASPER Crypto/FFT engine, up to 256 KB of
on-chip SRAM, up to 512 KB on-chip flash, PRINCE module for on-the-fly flash
encryption/decryption, high-speed and full-speed USB host and device interface with
crystal-less operation for full-speed, SD/MMC/SDIO interface, five general-purpose
timers, one SCTimer/PWM, one RTC/alarm timer, one 24-bit Multi-Rate Timer (MRT), a
Windowed Watchdog Timer (WWDT), nine flexible serial communication peripherals
(which can be configured as a USART, SPI, high speed SPI, I
2
C, or I
2
S interface),
Programmable Logic Unit (PLU), one 16-bit 1.0 Msamples/sec ADC, comparator, and
temperature sensor.
To support security requirements, the LPC55S2x/LPC552x also offers support for secure
boot, HASH, AES, RSA, UUID, dynamic encrypt and decrypt, debug authentication, and
TBSA compliance.
2. Features and benefits
ARM Cortex-M33 core (r0p3):
Running at a CPU frequency of up to 150 MHz
Memory Protection Unit (MPU).
ARM Cortex M33 built-in Nested Vectored Interrupt Controller (NVIC).
Non-maskable Interrupt (NMI) input with a selection of sources.
Serial Wire Debug with eight breakpoints and four watch points. Includes Serial
Wire Output for enhanced debug capabilities.
System tick timer.
CASPER Crypto co-processor is provided to enable hardware acceleration for various
functions required for certain asymmetric cryptographic algorithms, such as, Elliptic
Curve Cryptography (ECC).
On-chip memory:
Up to 512 KB on-chip flash program memory with flash accelerator and 256 byte
page erase and write.
Up to 256 KB total SRAM consisting of 32 KB SRAM on Code Bus, 208 KB SRAM
on System Bus (192 KB is contiguous), and additional 16 KB USB SRAM on
System Bus which can be used by the USB interface or for general purpose use.
NXP Semiconductors
LPC55S2x/LPC552x
32-bit ARM Cortex-M33 microcontroller
PRINCE module for real-time encryption of data being written to on-chip flash and
decryption of encrypted flash data during read to allow asset protection, such as
securing application code, and enabling secure flash update.
On-chip ROM bootloader supports:
Booting of images from on-chip flash
Supports CRC32 image integrity checking.
Supports flash programming through In System Programming (ISP) commands
over following interfaces: USB0/1 interfaces using HID Class device, UART
interface (Flexcomm 0) with auto baud, SPI slave interfaces (Flexcomm 3 or 9)
using mode 3 (CPOL = 1 and CPHA = 1), and I2C slave interface (Flexcomm 1)
ROM API functions: Flash programming API, Power control API, and Secure
firmware update API using NXP Secure Boot file format, version 2.0 (SB2 files).
Supports booting of images from PRINCE encrypted flash regions.
Support NXP Debug Authentication Protocol version 1.0 (RSA-2048) and 1.1
(RSA-4096).
Supports setting a sealed part to Fault Analysis mode through Debug
authentication.
Secure Boot support:
Uses RSASSA-PKCS1-v1_5 signature of SHA256 digest as cryptographic
signature verification.
Supports RSA-2048 bit public keys (2048 bit modulus, 32-bit exponent).
Supports RSA-4096 bit public keys (4096 bit modulus, 32-bit exponent).
Uses x509 certificate format to validate image public keys.
Supports up to four revocable Root of Trust (RoT) or Certificate Authority keys,
Root of Trust establishment by storing the SHA-256 hash digest of the hashes of
four RoT public keys in protected flash region (PFR).
Supports anti-rollback feature using image key revocation and supports up to 16
Image key certificates revocations using Serial Number field in x509 certificate.
Serial interfaces:
Flexcomm Interface contains up to nine serial peripherals (Flexcomm Interface 0-7
and Flexcomm Interface 8). Each Flexcomm Interface (except flexcomm 8, which
is dedicated for high-speed SPI) can be selected by software to be a USART, SPI,
I
2
C, and I
2
S interface. Each Flexcomm Interface includes a FIFO that supports
USART, SPI, and I
2
S. A variety of clocking options are available to each Flexcomm
Interface, including a shared fractional baud-rate generator, and time-out
feature.Flexcomm interfaces 0 to 7 each provide one channel pair of I
2
S.
I
2
C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to
1Mbit/s and with multiple address recognition and monitor mode. Two sets of true
I
2
C pads also support high-speed Mode (3.4 Mbit/s) as a slave.
USB 2.0 full speed host/device controller with on-chip PHY and dedicated DMA
controller supporting crystal-less operation in device mode using software library
example in technical note (TN00063).
USB 2.0 high-speed host/device controller with on-chip high-speed PHY.
Digital peripherals:
DMA0 controller with 23 channels and up to 22 programmable triggers, able to
access all memories and DMA-capable peripherals.
DMA1 controller with 10 channels and up to 15 programmable triggers, able to
access all memories and DMA-capable peripherals.
LPC55S2x/LPC552x
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2019. All rights reserved.
Product data sheet
Rev. 1.5 — 17 October 2019
2 of 126
NXP Semiconductors
LPC55S2x/LPC552x
32-bit ARM Cortex-M33 microcontroller
Secured digital input/output (SD/MMC and SDIO) card interface with DMA support.
SDIO with support for up to two cards. Supported card types are MMC, SDIO, and
CE-ATA. Supports SD2.0, and SDR25 (52MHz).
CRC engine block can calculate a CRC on supplied data using one of three
standard polynomials with DMA support.
Up to 64 General-Purpose Input/Output (GPIO) pins.
GPIO registers are located on the AHB for fast access. The DMA supports GPIO
ports.
Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising,
falling or both input edges.
Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical
(AND/OR) combination of input states.
I/O pin configuration with support for up to 16 function options.
Programmable Logic Unit (PLU) to create small combinatorial and/or sequential
logic networks including state machines.
Security Features:
AES-256 encryption/decryption engine with keys fed directly from PUF or a
software supplied key
Secure Hash Algorithm (SHA2) module supports secure boot with dedicated DMA
controller.
Physical Unclonable Function (PUF) using dedicated SRAM for silicon fingerprint.
PUF can generate, store, and reconstruct key sizes from 64 to 4096 bits. Includes
hardware for key extraction.
True Random Number Generator (TRNG).
128 bit unique device serial number for identification (UUID).
Secure GPIO.
Timers:
Five 32-bit standard general purpose asynchronous timers/counters, which support
up to four capture inputs and four compare outputs, PWM mode, and external
count input. Specific timer events can be selected to generate DMA requests.
One SCTimer/PWM with 8 input and 10 output functions (including 16 capture and
match registers). Inputs and outputs can be routed to or from external pins and
internally to or from selected peripherals. Internally, the SCTimer/PWM supports 16
captures/matches, 16 events, and 32 states.
32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power
domain. Another timer in the RTC can be used for wake-up from all low power
modes including deep power-down, with 1 ms resolution. The RTC is clocked by
the 32 kHz FRO or 32.768 kHz external crystal.
Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at
up to four programmable, fixed rates.
Windowed Watchdog Timer (WWDT) with FRO 1 MHz as clock source.
The Micro-Tick Timer running from the watchdog oscillator can be used to wake-up
the device from sleep and deep-sleep modes. Includes 4 capture registers with pin
inputs.
42-bit free running OS Timer as continuous time-base for the system, available in
any reduced power modes. It runs on 32kHz clock source, allowing a count period
of more than 4 years.
LPC55S2x/LPC552x
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2019. All rights reserved.
Product data sheet
Rev. 1.5 — 17 October 2019
3 of 126
NXP Semiconductors
LPC55S2x/LPC552x
32-bit ARM Cortex-M33 microcontroller
Analog peripherals:
16-bit ADC with five differential channel pair (or 10 single-ended channels), and
with multiple internal and external trigger inputs and sample rates of up to 1.0
MSamples/sec. The ADC supports two independent conversion sequences.
Integrated temperature sensor connected to the ADC.
Comparator with five input pins and external or internal reference voltage.
Clock generation:
Internal Free Running Oscillator (FRO). This oscillator provides a selectable 96
MHz output, and a 12 MHz output (divided down from the selected higher
frequency) that can be used as a system clock. The FRO is trimmed to +/- 2%
accuracy over the entire voltage and temperature range.
32 kHz Internal Free Running Oscillator FRO. The FRO is trimmed to +/- 65%
accuracy over the entire voltage and temperature range.
Internal low power oscillator (FRO 1 MHz) trimmed to +/- 15% accuracy over the
entire voltage and temperature range.
Crystal oscillator with an operating frequency of 12 MHz to 32 MHz. Option for
external clock input (bypass mode) for clock frequencies of up to 24 MHz.
Crystal oscillator with 32.768 KHz operating frequency. Option for external clock
input (bypass mode) for clock frequencies of up to 100 kHz.
PLL0 and PLL1 allows CPU operation up to the maximum CPU rate without the
need for a high-frequency external clock. PLL0 and PLL1 can run from the internal
FRO 12 MHz output, the external oscillator, internal FRO 1 MHz output, or the
32.768 KHz RTC oscillator.
Clock output function with divider to monitor internal clocks.
Frequency measurement unit for measuring the frequency of any on-chip or
off-chip clock signal.
Power-saving modes and wake-up:
Integrated PMU (Power Management Unit) to minimize power consumption.
Reduced power modes: Sleep, deep-sleep with RAM retention, power-down with
RAM retention and CPU retention, and deep power-down with RAM retention.
Configurable wake-up options from peripherals interrupts.
The Micro-Tick Timer running from the watchdog oscillator, and the Real-Time
Clock (RTC) running from the 32.768 kHz clock, can be used to wake-up the
device from sleep and deep-sleep modes.
Power-On Reset (POR).
Brown-Out Detectors (BOD) for VBAT_DCDC for forced reset or interrupt.
Operating from internal DC-DC converter.
Single power supply 1.8 V to 3.6 V.
JTAG boundary scan supported.
Operating temperature range
40
°C to +105 °C.
Available in HLQFP100, HTQFP64, and VFBGA98 packages.
LPC55S2x/LPC552x
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2019. All rights reserved.
Product data sheet
Rev. 1.5 — 17 October 2019
4 of 126
NXP Semiconductors
LPC55S2x/LPC552x
32-bit ARM Cortex-M33 microcontroller
3. Ordering information
Table 1.
Ordering information
Package
Name
Description
Version
Type number
LPC55S28JBD100 HLQFP100 plastic low profile quad flat package; 100 leads; body 14
14
0.5mm pitch SOT1570-3
LPC55S26JBD100 HLQFP100 plastic low profile quad flat package; 100 leads; body 14
14
0.5mm pitch SOT1570-3
LPC55S28JEV98
LPC55S26JEV98
LPC55S28JBD64
LPC55S26JBD64
LPC5528JBD100
LPC5526JBD100
LPC5528JEV98
LPC5526JEV98
LPC5528JBD64
LPC5526JBD64
VFBGA98
VFBGA98
HTQFP64
HTQFP64
thin fine-pitch ball grid array package; 98 balls; body 7‘ 7‘ 0.5 mm
thin fine-pitch ball grid array package; 98 balls; body 7‘ 7‘ 0.5 mm
SOT1982-1
SOT1982-1
thin fine-pitch ball grid array package; 64 leads; body 10
10
0.5mm pitch SOT855-5
thin fine-pitch ball grid array package; 64 leads; body 10
10
0.5mm pitch SOT855-5
HLQFP100 plastic low profile quad flat package; 100 leads; body 14
14
0.5mm pitch SOT1570-3
HLQFP100 plastic low profile quad flat package; 100 leads; body 14
14
0.5mm pitch SOT1570-3
VFBGA98
VFBGA98
HTQFP64
HTQFP64
thin fine-pitch ball grid array package; 98 balls; body 7‘ 7‘ 0.5 mm
thin fine-pitch ball grid array package; 98 balls; body 7‘ 7‘ 0.5 mm
SOT1982-1
SOT1982-1
thin fine-pitch ball grid array package; 64 leads; body 10
10
0.5mm pitch SOT855-5
thin fine-pitch ball grid array package; 64 leads; body 10
10
0.5mm pitch SOT855-5
3.1 Ordering options
Table 2.
Ordering options
Max CPU Frequency
(MHz)
Type number
Total SRAM/KB
PUF Controller
Secure boot
HASH-AES
Flash/KB
CASPER
PRINCE
LPC55S28JBD100
LPC55S26JBD100
LPC55S28JEV98
LPC55S26JEV98
LPC55S28JBD64
LPC55S26JBD64
LPC5528JBD100
LPC5526JBD100
LPC5528JEV98
LPC5526JEV98
LPC5528JBD64
LPC5526JBD64
150
150
150
150
150
150
150
150
150
150
150
150
yes
yes
yes
yes
yes
yes
-
-
-
-
-
-
512
256
512
256
512
256
512
256
512
256
512
256
256
144
256
144
256
144
256
144
256
144
256
144
yes
yes
yes
yes
yes
yes
-
-
-
-
-
-
yes
yes
yes
yes
yes
yes
-
-
-
-
-
-
yes
yes
yes
yes
yes
yes
-
-
-
-
-
-
yes
yes
yes
yes
yes
yes
-
-
-
-
-
-
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
FS + HS
FS + HS
FS + HS
FS + HS
FS + HS
FS + HS
FS + HS
FS + HS
FS + HS
FS + HS
FS + HS
FS + HS
LPC55S2x/LPC552x
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2019. All rights reserved.
Product data sheet
Rev. 1.5 — 17 October 2019
5 of 126
GPIO
64
64
64
64
36
36
64
64
64
64
36
36
SDIO
USB
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