PC7448FGH1267ND datasheet, PDF

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PC7448FGH1267ND: DescriptionRISC Microprocessor, 32-Bit, 1267MHz, CMOS, CBGA360, 25 X 25 MM, 2.80 MM HEIGHT, 1.27 MM PITCH, CERAMIC, HITCE, BGA-360; CategoryThe embedded processor and controller Microcontrollers and processors; File Size500KB，57 Pages; Manufacturere2v technologies

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PC7448FGH1267ND Overview

RISC Microprocessor, 32-Bit, 1267MHz, CMOS, CBGA360, 25 X 25 MM, 2.80 MM HEIGHT, 1.27 MM PITCH, CERAMIC, HITCE, BGA-360

PC7448FGH1267ND Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	e2v technologies
Parts packaging code	BGA
package instruction	BGA, BGA360,19X19,50
Contacts	360
Reach Compliance Code	compliant
ECCN code	3A001.A.3
Address bus width	36
bit size	32
boundary scan	YES
maximum clock frequency	200 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CBGA-B360
length	25 mm
low power mode	NO
Number of terminals	360
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	BGA
Encapsulate equivalent code	BGA360,19X19,50
Package shape	SQUARE
Package form	GRID ARRAY
power supply	1.05,1.5/2.5 V
Certification status	Not Qualified
Maximum seat height	2.8 mm
speed	1267 MHz
Maximum supply voltage	1.1 V
Minimum supply voltage	1 V
Nominal supply voltage	1.05 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	25 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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PC7448

PowerPC 7448 RISC Microprocessor

Datasheet

Features

•

3000 Dhrystone 2.1 MIPS at 1.3 GHz

Selectable Bus Clock (30 CPU Bus Dividers up to 28x)

Selectable MPx/60x Interface Voltage (1.5V; 1.8V; 2.5V)

Typically 10W at 1.25 GHz at V

= 1.1V

Full Operating Conditions

Nap, Doze and Sleep Power Saving Modes

Superscalar (Four Instructions Fetched Per Clock Cycle)

4 GB Direct Addressing Range

Virtual Memory: 4 Hexabytes (2

)

64-bit Data and 36-bit Address Bus Interface

Integrated L1: 32 KB Instruction and 32 KB Data Cache

Integrated L2: 1 MB with ECC

11 Independent Execution Units and 3 Register Files

Write-back and Write-through Operations

INT

Max = 1267 MHz

BUS

Max = 133 MHz/166 MHz and 200 MHz

Description

This document is primarily concerned with the Power Architecture

™

PC7448. The PC7448 is an implementation of the

PowerPC microprocessor family of Reduced Instruction Set Computer (RISC) microprocessors. This document describes

pertinent electrical and physical characteristics of the PC7448. For information regarding specific PC7448 part numbers

covered by this document and part numbers covered by other documents,

See “Ordering Information” on page 52.”

For

functional characteristics of the processor, refer to the

PC7450 RISC Microprocessor Family Reference Manual.

Screening

•

Full Military Temperature Range (T

= –55° C, T

= +125° C)

•

Industrial Temperature Range (T

= –40° C, T

= +110° C)

Visit our website: www.e2v.com

for the latest version of the datasheet

e2v semiconductors SAS 2009

0814G–HIREL–04/09

PC7448

Note that the PC7448 is a footprint-compatible, drop-in replacement in an PC7447A application if the

core voltages are identical.

2. Features

This section summarizes features of the PC7448 implementation of the PowerPC architecture.

Major features of the PC7448 are as follows:

• High-performance, superscalar microprocessor

Up to four instructions can be fetched from the instruction cache at a time

Up to three instructions plus a branch instruction can be dispatched to the issue queues at a time

Up to 12 instructions can be in the Instruction Queue (IQ)

Up to 16 instructions can be at some stage of execution simultaneously

Single-cycle execution for most instructions

One instruction per clock cycle throughput for most instructions

Seven-stage pipeline control

• Eleven independent execution units and three register files

Branch Processing Unit (BPU) features static and dynamic branch prediction

– 128-entry (32-set, four-way set-associative) Branch Target Instruction Cache (BTIC), a

cache of branch instructions that have been encountered in branch/loop code sequences. If

a target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than

it can be made available from the instruction cache. Typically, a fetch that hits the BTIC

provides the first four instructions in the target stream

– 2048-entry Branch History Table (BHT) with 2 bits per entry for four levels of prediction: not

taken, strongly not taken, taken, and strongly taken

– Up to three outstanding speculative branches

– Branch instructions that do not update the count register (CTR) or Link Register (LR) are

often removed from the instruction stream

– Eight-entry link register stack to predict the target address of branch conditional to link

Four Integer Units (IUs) that share 32 GPRs for integer operands

– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except

multiply, divide, and move to/from special-purpose register instructions

– IU2 executes miscellaneous instructions, including the CR logical operations, integer

multiplication and division instructions, and move to/from special-purpose register

instructions

Five-stage FPU and 32-entry FPR file

– Fully IEEE

754-1985 – compliant FPU for both single- and double-precision operations

– Supports non-IEEE mode for time-critical operations

– Hardware support for denormalized numbers

– Thirty-two 64 bits FPRs for single or double-precision operands

Four vector units and 32-entry Vector Register file (VRs).

0814G–HIREL–04/09

e2v semiconductors SAS 2009

PC7448

– Vector Permute Unit (VPU)

– Vector Integer Unit 1 (VIU1) handles short-latency AltiVec

integer instructions, such as

vector add instructions (for example,

vaddsbs, vaddshs,

and

vaddsws)

– Vector Integer Unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as

vector multiply add instructions (for example,

vmhaddshs, vmhraddshs,

and

vmladduhm)

– Vector Floating-point Unit (VFPU)

Three-stage Load/Store Unit (LSU)

– Supports integer, floating-point, and vector instruction load/store traffic

– Four-entry Vector Touch Queue (VTQ) supports all four architected AltiVec data stream

operations

– Three-cycle GPR and AltiVec load latency (byte, half word, word, vector) with one-cycle

throughput

– Four-cycle FPR load latency (single, double) with one-cycle throughput

– No additional delay for misaligned access within double-word boundary

– A dedicated adder calculates Effective Addresses (EAs)

– Supports store gathering

– Performs alignment, normalization, and precision conversion for floating-point data

– Executes cache control and TLB instructions

– Performs alignment, zero padding, and sign extension for integer data

– Supports hits under misses (multiple outstanding misses)

– Supports both big and little-endian modes, including misaligned little-endian accesses

• Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions,

respectively, in a cycle. Instruction dispatch requires the following:

Instructions can only be dispatched from the three lowest IQ entries, IQ0, IQ1, and IQ2

A maximum of three instructions can be dispatched to the issue queues per clock cycle

Space must be available in the CQ for an instruction to dispatch (this includes instructions that are

assigned a space in the CQ but not in an issue queue)

• Rename buffers

16 GPR rename buffers

16 FPR rename buffers

16 VR rename buffers

• Dispatch unit

Decode/dispatch stage fully decodes each instruction

• Completion unit

Retires an instruction from the 16-entry Completion Queue (CQ) when all instructions ahead of it

have been completed, the instruction has finished executing, and no exceptions are pending

Guarantees sequential programming model (precise exception model)

Monitors all dispatched instructions and retires them in order

Tracks unresolved branches and flushes instructions after a mispredicted branch

0814G–HIREL–04/09

e2v semiconductors SAS 2009

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