CBTL06DP211
DisplayPort Gen1 2 : 1 multiplexer
Rev. 1 — 21 February 2011
Product data sheet
1. General description
CBTL06DP211 is a multi-channel high-speed multiplexer meant for DisplayPort (DP)
v1.1a or Embedded DisplayPort applications operating at data rate of 1.62 Gbit/s or
2.7 Gbit/s. It is designed using NXP proprietary high-bandwidth pass-gate technology and
it can be used for 1 : 2 switching or 2 : 1 multiplexing of four high-speed differential
AC-coupled DP channels. Further, it is capable of switching/multiplexing of Hot Plug
Detect (HPD) signal as well as Auxiliary (AUX) and Display Data Channel (DDC) signals.
In order to support GPUs/CPUs that have dedicated AUX and DDC I/Os, CBTL06DP211
provides an additional level of multiplexing of AUX and DDC signals delivering true
flexibility and choice.
CBTL06DP211 consumes very low current in operational mode (less than 1 mA typical)
and provides for a shutdown function (ultra low current consumption less than 10
μA)
to
support power-sensitive or battery-powered applications. It is designed for delivering
optimum performance at DP data rates of 1.62 Gbit/s and 2.7 Gbit/s.
A typical application of CBTL06DP211 is on motherboards where one of two GPU display
sources needs to be selected to connect to a display sink device or connector. A controller
chip selects which path to use by setting a select signal HIGH or LOW. Due to the
non-directional nature of the signal paths (which use high-bandwidth pass-gate
technology), the CBTL06DP211 can also be used in the reverse topology, e.g., to connect
one display source device to one of two display sink devices or connectors.
Optionally, the CBTL06DP211 can be used in conjunction with an HDMI/DVI level shifter
device (PTN3360A/B or PTN3360D) to allow for DisplayPort as well as HDMI/DVI
connectivity.
2. Features and benefits
1 : 2 switching or 2 : 1 multiplexing of DisplayPort (v1.1a - 1.62 Gbit/s or 2.7 Gbit/s)
4 high-speed differential channels with 2 : 1 multiplexing/switching for DisplayPort
signals
1 channel with 4 : 1 multiplexing/switching for AUX differential signals and DDC
single-ended clock and data signals
1 channel with 2 : 1 multiplexing/switching for single-ended HPD signals
High-bandwidth analog pass-gate technology
Very low lane intra-pair skew (5 ps typical)
Very low inter-pair skew (< 180 ps)
Switch/multiplexer position select CMOS input
Shutdown mode CMOS input
Shutdown mode delivers ultra low power consumption
NXP Semiconductors
CBTL06DP211
DisplayPort Gen1 2 : 1 multiplexer
DDC and AUX ports tolerant to being pulled to +5 V via 2.2 kΩ resistor
Supports HDMI/DVI incorrect dongle connection
Single 3.3 V power supply
Very low operation current of 0.2 mA typical
Very low shutdown current of < 10
μA
ESD 8 kV HBM, 1 kV CDM
ESD 2 kV HBM, 500 V CDM for control pins
Available in 5 mm
×
5 mm, 0.5 mm ball pitch TFBGA48 package
3. Applications
Motherboard applications requiring DisplayPort and PCI Express
switching/multiplexing
Docking stations
Notebook computers
Chip sets requiring flexible allocation of PCI Express or DisplayPort I/O pins to board
connectors
4. Ordering information
Table 1.
Ordering information
Solder process
Pb-free (SnAgCu
solder compound)
Package
Name
CBTL06DP211EE
TFBGA48
Description
plastic thin fine-pitch ball grid array package;
48 balls; body 5
×
5
×
0.8 mm
[1]
Version
SOT918-1
Type number
[1]
Total height including solder balls after printed-circuit board mounting = 1.15 mm.
CBTL06DP211
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
2 of 18
NXP Semiconductors
CBTL06DP211
DisplayPort Gen1 2 : 1 multiplexer
5. Functional diagram
VDD
CBTL06DP211
4
IN1_n+
IN1_n−
IN2_n+
IN2_n−
0
4
4
OUT_n+
OUT_n−
1
AUX1+
AUX1−
AUX2+
AUX2−
DDC_CLK1
DDC_DAT1
DDC_CLK2
DDC_DAT2
00
10
AUX+ or DDC clock
AUX− or DDC data
AUX+
AUX−
01
11
HPD_1
0
HPDIN
HPD_2
1
GPU_SEL
DDC_AUX_SEL
TST0
XSD
GND
002aag002
Fig 1.
Functional diagram
CBTL06DP211
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
3 of 18
NXP Semiconductors
CBTL06DP211
DisplayPort Gen1 2 : 1 multiplexer
6. Pinning information
6.1 Pinning
ball A1
index area
CBTL06DP211EE
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
002aag003
Transparent top view
Fig 2.
Pin configuration for TFBGA48
1
A
B
C
D
E
F
G
H
J
AUX−
HPDIN
OUT_1−
OUT_2−
OUT_3−
GPU_SEL
OUT_0−
2
VDD
OUT_0+
DDC_AUX
_SEL
OUT_1+
OUT_2+
OUT_3+
TST0
AUX+
HPD_1
3
4
IN1_0−
5
IN1_1−
IN1_1+
6
IN1_2−
IN1_2+
7
8
IN1_3+
9
IN1_3−
IN2_0−
GND
IN1_0+
XSD
IN2_0+
GND
IN2_1+
IN2_2+
IN2_3+
GND
IN2_1−
IN2_2−
IN2_3−
HPD_2
GND
VDD
DDC_CLK2
DDC_DAT2
AUX2+
AUX2−
GND
DDC_CLK1
DDC_DAT1
AUX1+
AUX1−
002aag004
Transparent top view
Fig 3.
Ball mapping
CBTL06DP211
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
4 of 18
NXP Semiconductors
CBTL06DP211
DisplayPort Gen1 2 : 1 multiplexer
6.2 Pin description
Table 2.
Symbol
GPU_SEL
Pin description
Ball
A1
Type
3.3 V low-voltage CMOS
single-ended input
Description
Selects between two multiplexer/switch paths. When HIGH, path 2
left-side is connected to its corresponding right-side I/O. When
LOW, path 1 left-side is connected to its corresponding right-side
I/O.
Selects between DDC and AUX paths. When HIGH, the
DDC_CLKn and DDC_DATn I/Os are connected to their respective
AUX terminals. When LOW, the AUX+ and AUX− I/Os are
connected to their respective AUX terminals.
Shutdown pin. Should be driven HIGH or connected to VDD for
normal operation. When LOW, all paths are switched off
(non-conducting) and supply current consumption is minimized.
Test pin for NXP use only. Should be tied to ground in normal
operation.
Four high-speed differential pairs for DisplayPort or PCI Express
signals, path 1, left-side.
DDC_AUX_SEL
C2
3.3 V low-voltage CMOS
single-ended input
XSD
B7
3.3 V low-voltage CMOS
single-ended input
3.3 V low-voltage CMOS
single-ended input
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
TST0
IN1_0+
IN1_0−
IN1_1+
IN1_1−
IN1_2+
IN1_2−
IN1_3+
IN1_3−
IN2_0+
IN2_0−
IN2_1+
IN2_1−
IN2_2+
IN2_2−
IN2_3+
IN2_3−
OUT_0+
OUT_0−
OUT_1+
OUT_1−
OUT_2+
OUT_2−
OUT_3+
OUT_3−
AUX1+
AUX1−
AUX2+
AUX2−
G2
B4
A4
B5
A5
B6
A6
A8
A9
B8
B9
D8
D9
E8
E9
F8
F9
B2
B1
D2
D1
E2
E1
F2
F1
H9
J9
H6
J6
Four high-speed differential pairs for DisplayPort or PCI Express
signals, path 2, left-side.
Four high-speed differential pairs for DisplayPort or PCI Express
signals, right-side.
High-speed differential pair for AUX signals, path 1, left-side.
High-speed differential pair for AUX signals, path 2, left-side.
CBTL06DP211
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
5 of 18
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