X22C12
1K Bit
X22C12
Nonvolatile Static RAM
DESCRIPTION
256 x 4
FEATURES
•
•
•
•
•
•
•
•
High Performance CMOS
—150ns RAM Access Time
High Reliability
—Store Cycles: 1,000,000
—Data Retention: 100 Years
Low Power Consumption
—Active: 40mA Max.
—Standby: 100
µ
A Max.
Infinite Array Recall, RAM Read and Write Cycles
Nonvolatile Store Inhibit: V
CC
= 3.5V Typical
Fully TTL and CMOS Compatible
JEDEC Standard 18-Pin 300-mil DIP
100% Compatible with X2212
—With Timing Enhancements
The X22C12 is a 256 x 4 CMOS NOVRAM featuring a
high-speed static RAM overlaid bit-for-bit with a non-
volatile E
2
PROM. The NOVRAM design allows data to
be easily transferred from RAM to E
2
PROM (STORE)
and from E
2
PROM to RAM (RECALL). The STORE
operation is completed within 5ms or less and the
RECALL is completed within 1µs.
Xicor NOVRAMs are designed for unlimited write opera-
tions to the RAM, either RECALLs from E
2
PROM or
writes from the host. The X22C12 will reliably endure
1,000,000 STORE cycles. Inherent data retention is
greater than 100 years.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
PLASTIC DIP
CERDIP
STORE
A7
A4
A3
A2
A1
A0
CS
VSS
STORE
1
2
3
4
5
6
7
8
9
18
17
16
15
X22C12 14
13
12
11
10
VCC
A6
A5
I/O4
I/O3
I/O2
I/01
WE
RECALL
3817 FHD F02
2
NONVOLATILE E PROM
MEMORY ARRAY
A0
A1
A2
A3
A4
STORE
RECALL
I/O1
I/O2
I/O3
I/O4
INPUT
DATA
CONTROL
COLUMN SELECT
CONTROL
LOGIC
VCC
VSS
ROW
SELECT
STATIC RAM
MEMORY ARRAY
ARRAY
RECALL
COLUMN
I/O CIRCUITS
SOIC
A7
A4
A3
A2
A1
A0
CS
VSS
1
2
3
4
5
6
7
8
9
10
X22C12
20
19
18
17
16
15
14
13
12
11
VCC
A6
A5
I/O4
NC
NC
I/O3
I/O2
I/O1
WE
A7
A6
A5
CS
WE
3817 FHD F01
STORE
RECALL
3815 FHD F10.1
© Xicor, Inc. 1991, 1995 Patents Pending
3817-2.4 7/30/96 T0/C0/D1 SH
1
Characteristics subject to change without notice
X22C12
PIN DESCRIPTIONS AND DEVICE OPERATION
Addresses (A
0
–A
7
)
The address inputs select a 4-bit memory location
during a read or write operation.
Chip Select (CS)
The Chip Select input must be LOW to enable read or
write operations with the RAM array.
CS
HIGH will place
the I/O pins in the high impedance state.
Write Enable (WE)
The Write Enable input controls the I/O buffers, deter-
mining whether a RAM read or write operation is en-
abled. When
CS
is LOW and
WE
is HIGH, the I/O pins
will output data from the selected RAM address loca-
tions. When both
CS
and
WE
are LOW, data presented
at the I/O pins will be written to the selected address
location.
Data In/Data Out (I/O
1
–I/O
4
)
Data is written to or read from the X22C12 through the
I/O pins. The I/O pins are placed in the high impedance
state when either
CS
is HIGH or during either a store or
recall operation.
STORE
The
STORE
input, when LOW, will initiate the transfer of
the entire contents of the RAM array to the E
2
PROM
array. The
WE
and
RECALL
inputs are inhibited during
the store cycle. The store operation is completed in 5ms
or less.
A store operation has priority over RAM read/write
operations. If
STORE
is asserted during a read opera-
tion, the read will be discontinued. If
STORE
is asserted
during a RAM write operation, the write will be immedi-
ately terminated and the store performed. The data at
the RAM address that was being written will be unknown
in both the RAM and E
2
PROM arrays.
RECALL
The
RECALL
input, when LOW, will initiate the transfer
of the entire contents of the E
2
PROM array to the RAM
array. The transfer of data will be completed in 1µs or
less.
An array recall has priority over RAM read/write opera-
tions and will terminate both operations when
RECALL
is asserted.
RECALL
LOW will also inhibit the
STORE
input.
Automatic Recall
Upon power-up the X22C12 will automatically recall
data from the E
2
PROM array into the RAM array.
Write Protection
The X22C12 has three write protect features that are
employed to protect the contents of the nonvolatile
memory.
• V
CC
Sense—All functions are inhibited when V
CC
is
<3.5V typical.
• Write Inhibit—Holding either
STORE
HIGH or
RECALL
LOW during power-up or power-down will
prevent an inadvertent store operation and E
2
PROM
data integrity will be maintained.
• Noise Protection—A
STORE
pulse of typically less
than 20ns will not initiate a store cycle.
PIN NAMES
Symbol
A
0
–A
7
I/O
1
–I/O
4
WE
CS
RECALL
STORE
V
CC
V
SS
NC
Description
Address Inputs
Data Inputs/Outputs
Write Enable
Chip Select
Recall
Store
+5V
Ground
No Connect
3817 PGM T01
2
X22C12
ABSOLUTE MAXIMUM RATINGS
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to V
SS .......................................
–1V to +7V
D.C. Output Current ............................................ 5mA
Lead Temperature
(Soldering, 10 seconds) .............................. 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Military
Min.
0°C
–40°C
–55°C
Max.
+70°C
+85°C
+125°C
3817 PGM T12.1
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Supply Voltage
X22C12
Limits
5V
±10%
3817 PGM T13
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
l
CC
Parameter
V
CC
Supply Current,
RAM Read/Write
V
CC
Standby Current
(TTL Inputs)
V
CC
Standby Current
(CMOS Inputs)
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Min.
Max.
40
Units
mA
Test Conditions
CS
= V
IL
, I/Os = Open, All Others =
V
IH
, Addresses = 0.4V/2.4V Levels @
f = 8MHz
Store or Recall Functions Not Active,
I/Os = Open, All Other Inputs = V
IH
Store or Recall functions Not Active,
I/Os = Open, All Other Inputs =
V
CC
–0.3V
V
IN
= V
SS
to V
CC
V
OUT
= V
SS
to V
CC
I
SB1
I
SB2
2
100
mA
µA
I
LI
I
LO
V
lL(2)
V
IH(2)
V
OL
V
OH
–1
2
2.4
10
10
0.8
V
CC
+ 1
0.4
µA
µA
V
V
V
V
I
OL
= 4.2mA
I
OH
= –2mA
3817 PGM T02.3
CAPACITANCE
T
A
= +25°C, f = 1MHz, V
CC
= 5V
Symbol
C
I/O(1)
C
IN(1)
Parameter
Input/Output Capacitance
Input Capacitance
Max.
8
6
Units
pF
pF
Test Conditions
V
I/O
= 0V
V
IN
= 0V
3815 PGM T03.1
Notes:
(1) This parameter is periodically sampled and not 100% tested.
(2) V
IL
min. and V
IH
max. are for reference only and are not tested.
3
X22C12
MODE SELECTION
CE
H
L
L
L
X
H
X
H
WE
X
H
L
L
H
X
H
X
RECALL
H
H
H
H
L
L
H
H
STORE
H
H
H
H
H
H
L
L
I/O
Output High Z
Output Data
Input Data High
Input Data Low
Output High Z
Output High Z
Output High Z
Output High Z
Mode
Not Selected
(3)
Read RAM
Write “1” RAM
Write “0” RAM
Array Recall
Array Recall
Nonvolatile Store
(4)
Nonvolatile Store
(4)
3817 PGM T05.1
ENDURANCE AND DATA RETENTION
Parameter
Endurance
Store Cycles
Data Retention
POWER-UP TIMING
Symbol
t
PUR(5)
t
PUW(5)
Parameter
Power-up to Read Operation
Power-up to Write or Store Operation
Max.
100
5
Units
µs
ms
3817 PGM T07
Min.
100,000
1,000,000
100
Units
Data Changes Per Bit
Store Cycles
Years
3817 PGM T06
EQUIVALENT A.C. LOAD CIRCUIT
5V
A.C. CONDITIONS OF TEST
Input Pulse Levels
Input Rise and
Fall Times
Input and Output
Timing Levels
100pF
0V to 3V
10ns
1.5V
3817 PGM T04.1
919Ω
OUTPUT
497Ω
3815 FHD F09.1
Notes:
(3) Chip is deselected but may be automatically completing a store cycle.
(4)
STORE
= LOW is required only to initiate the store cycle, after which the store cycle will be automatically completed
(e.g.
STORE
= X).
(5) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated. These
parameters are periodically sampled and not 100% tested.
4
X22C12
A.C. CHARACTERISTICS
(Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits
Symbol
t
RC
t
AA
t
CO
t
OH
t
LZ(6)
t
HZ(6)
Read Cycle
tRC
ADDRESS
tA
tCO
CS
tLZ
DATA I/O
DATA VALID
3817 FHD F03
Parameter
Read Cycle Time
Access Time
Chip Select to Output Valid
Output Hold from Address Change
Chip Select to Output in Low Z
Chip Deselect to Output in High Z
Min.
150
Max.
150
150
Units
ns
ns
ns
ns
ns
ns
3817 PGM T08
0
0
50
tOH
tHZ
Note:
(6) t
LZ
min. and t
HZ
min. are periodically sampled and not 100% tested.
5
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