SY89540U
Precision Low Jitter 4x4 LVDS Crosspoint
Switch with Internal Termination
General Description
The SY89540U is a low-jitter, low skew, high-speed
4x4 crosspoint switch optimized for precision telecom
and enterprise server/storage distribution applications.
The SY89540U guarantees data-rates up to 3.2Gbps
over temperature and voltage.
The SY89540U differential input includes Micrel’s
unique, 3-pin input termination architecture that
directly interfaces to any differential signal (AC or DC-
coupled) as small as 100mV (200mV
pp
) without any
level shifting or termination resistor networks in the
signal path. The LVDS compatible outputs maintain
extremely fast rise/fall times guaranteed to be less
than 120ps.
The SY89540U features a patent-pending isolation
design that significantly improves on channel-to-
channel crosstalk performance.
The SY89540U operates from a 2.5V ±5% supply and
is guaranteed over the full industrial temperature range
(–40°C to +85°C). The SY89540U is part of Micrel’s
®
high-speed, Precision Edge product line.
All support documentation can be found on Micrel’s
web site at
www.micrel.com.
Precision Edge
®
Features
• Provides crosspoint switching between any input
pairs to any output pair
• Patent pending, channel-to-channel isolation design
provides superior crosstalk performance
• Guaranteed AC performance over temperature and
voltage:
• DC-to-3.2Gbps throughput
– <480ps propagation delay
– <120ps rise/fall time
– <30ps output-to-output skew
• Ultra-low jitter design:
– 95fs RMS phase jitter (Typ)
– 0.7ps
RMS
crosstalk induced jitter
• Patent pending 50Ω input termination, extended
CMVR, and VT pin accepts DC- and AC-coupled
differential inputs
• 350mV LVDS output swing
• Power supply 2.5V ±5%
• –40°C to +85°C temperature range
• Available in 44-pin (7mm x 7mm) QFN package
• Pb-Free Green package
Typical Performance
Applications
• All SONET/SDH channel select applications
• All Fibre Channel multi-channel select applications
• All Gigabit Ethernet multi-channel select
applications
United States Patent No. RE44,134
Precision Edge is a registered trademark of Micrel, Inc.
Oct. 1, 2013
M9999-120607-C
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89540U
Functional Block Diagram
Oct., 1, 2013
2
M9999-120607-C
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89540U
Ordering Information
(1)
Part Number
SY89540UMY
SY89540UMYTR
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC electrical only.
2. Tape and Reel ordering option.
(2)
Package
Type
QFN-44
QFN-44
Temperature
Range
Industrial
Industrial
Package Marking
SY89540U with
Pb-Free bar-line indicator
SY89540U with
Pb-Free bar-line indicator
Lead
Finish
Pb-Free
Matte-Sn
Pb-Free
Matte-Sn
Pin Configuration
44-Pin QFN
Oct., 1, 2013
3
M9999-120607-C
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89540U
Pin Description
Pin Number
17, 15,
10, 8
4, 2
41, 39
16, 9,
3, 40
Pin Name
IN0, /IN0,
IN1, /IN1,
IN2, /IN2,
IN3, /IN3
VT0, VT1,
VT2, VT3
Pin Function
Differential Inputs: These input pairs are the differential signal inputs to the
device. Inputs accept AC- or DC-coupled signals as small as 100mV. Each pin
of a pair internally terminates to a VT pin through 50Ω. Note that these inputs
will default to an indeterminate state if left open. Please refer to the "Input
Interface Applications" section for more details.
Input Termination Center-Tap: Each side of the differential input pair terminates
to a VT pin. The VT pins provide a center-tap to a termination network for
maximum interface flexibility. See "Input Interface Applications" section for more
details.
Reference Voltage: This output biases to V
CC
–1.2V. It is used when AC-
coupling the inputs (IN, /IN). Connect VREF_AC to the VT pin. Bypass each
VREF-AC pin with a 0.01F low ESR capacitor. See "Input Interface
Applications" section for more details.
These single-ended TTL/CMOS-compatible inputs address the data inputs.
Note that these inputs are internally connected to a 25kΩ pull-up resistor and
will default to a logic HIGH state if left open.
These single-ended TTL/CMOS-compatible inputs address the data outputs.
Note that these inputs are internally connected to a 25kΩ pull-up resistor and
will default to logic HIGH state if left open.
These single-ended TTL/CMOS-compatible inputs control the transfer of the
addresses to the internal multiplexers. See "Address Tables" and "Timing
Diagram" sections for more details. Note that these inputs are internally
connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left
open.
Configuration Sequence
1. Load: Loads configuration into buffer, while Configuration Buffer holds
existing switch configuration.
2. Configuration: Loads new configuration into the Configuration Buffer and
updates switch configuration.
Buffer Mode
The SY89540U defaults to buffer mode (IN to Q) if the load and configuration
control signals are not exercised.
23, 24,
26, 27,
29, 30,
32, 33
6, 22, 25,
28, 31, 34
12, 13, 20,
21,35, 36,
43, 44
Q0, /Q0,
Q1, /Q1,
Q2, /Q2,
Q3, /Q3,
VCC
GND,
Exposed pad
Differential Outputs: These LVDS output pairs are the outputs of the device.
Please refer to the truth table below for details. Unused output pairs may be left
open. Each output is designed to drive 350mV into 100Ω across the pair.
14,
11,
1,
42
18, 19
VREF_AC0,
VREF_AC1,
VREF_AC2,
VREF_AC3
SIN0,
SIN1
SOUT0,
SOUT1
CONF,
LOAD
38, 37
5, 7
Positive power supply. Bypass with 0.1F//0.01F low ESR capacitors and
place as close to each V
CC
pin.
Ground. GND and EPad must both be connected to the same ground.
Oct., 1, 2013
4
M9999-120607-C
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89540U
Functional Description
Buffer Mode
SY89540 can be used as a 1:4 fanout buffer. This is
the default mode with LOAD and CONFIG being HIGH
when the device is first powered up. The SIN0 and
SIN1 inputs select the input signal that will be buffered.
Regardless of the output switch selection, the input
signal will be buffered to all four outputs.
Crosspoint Mode
SY89540 can be programmed to take differential input
signals from any input and buffer the signals to one or
more outputs. Prior to configuring SIN and SOUT,
LOAD and CONFIG must be LOW. To program the
desired I/O combination, follow the following
sequence:
1) Select the desired input with the SIN0 and
SIN1 inputs and the output with the SOUT0
and SOUT1.
2) Pulse the LOAD with a positive pulse to load
SIN and SOUT.
3) Pulse the CONFIG pin with a positive pulse to
latched the I/O configuration.
4) This method can be used to create
independent paths between inputs and
outputs. Below is the truth table to create a 4:4
buffer where IN0 -> Q3, IN1 -> Q2, IN2 -> Q1,
and IN3 -> Q0:
Input
SIN1
SIN0
SOUT1
The SY89540 can be switched from crosspoint mode
to a 1:4 fanout buffer simply by providing a LOW-to-
HIGH pulse to the LOAD and CONFIG pins. The input
configuration (SIN0:1) will select the desired input
signal while the output switch will buffer the selected
input signal. To get the same desired input to all four
outputs (1:4), LOAD and CONFIG must be repeated
four times to cover all outputs (i.e., SOUT0:1 must go
through all four output combinations, repeated by
LOAD and CONFIG).
SOUT0
Load
Config.
0
Output
Q3
Q2
Q1
IN0
IN1
0
0
0
1
1
1
1
0
0
0
0
0
IN2
IN3
1
1
0
1
0
0
1
0
0
0
0
Q0
Table 1. 4:4 Buffer Truth Table
Oct., 1, 2013
5
M9999-120607-C
hbwhelp@micrel.com
or (408) 955-1690
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