NOT RECOMMENDED FOR NEW DESIGNS
SY89809L
3.3V 1:9 High-Performance, Low-Voltage
Bus Clock Driver
General Description
The SY89809L is a High-Performance Bus Clock Driver
with 9 differential HSTL (High-Speed Transceiver Logic)
output pairs. The part is designed for use in low-voltage
(3.3V/1.8V) applications, which require a large number of
outputs to drive precisely aligned, ultra-low skew signals to
their destination. The input is multiplexed from either HSTL
or LVPECL (Low-Voltage Positive-Emitter-Coupled Logic)
by the CLK_SEL pin. The Output Enable (OE) is
synchronous so that the outputs will only be
enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse
when the device is enabled/disabled as can happen with
an asynchronous control.
The SY89809L features low pin-to-pin skew (50ps max.)
and low part-to-part skew (200ps max.)—performance
previously unachievable in a standard product having such
a high number of outputs. The SY89809L is available in a
single space saving package, enabling a lower overall cost
solution.
Datasheets and support documentation can be found on
Micrel’s web site at:
www.micrel.com.
Precision Edge
®
Features
•
•
•
•
•
•
•
•
3.3V core supply, 1.8V output supply for reduced power
LVPECL and HSTL inputs
9 differential HSTL (low-voltage swing) output pairs
HSTL outputs drive 50Ω-to-ground with no offset voltage
500MHz maximum clock frequency
Low part-to-part skew (200ps max.)
Low pin-to-pin skew (50ps max.)
Available in 32-pin TQFP
Applications
•
•
•
•
•
High-performance PCs
Workstations
Parallel processor-based systems
Other high-performance computing
Communications
Level
Direction
Input
Output
Input
Input
Signal
HSTL_CLK, /HSTL_CLK
Q0 – Q8, /Q0 – /Q8
LVPECL_CLK, /LVPECL_CLK
CLK_SEL, OE
Logic Symbol
HSTL
HSTL
LVPECL
LVCMOS/LVTTL
Table 1. Signal Groups
OE
0
0
1
1
(1)
CLK_SEL
0
1
0
1
Q0 – Q8
LOW
LOW
HSTL_CLK
LVPECL_CLK
/Q0 – /Q8
HIGH
HIGH
/HSTL_CLK
/LVPECL_CLK
Table 2. Truth Table
Note:
1. The OE (output enable) signal is synchronized with the low level of
the HSTL_CLK and LVPECL_CLK signal.
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
408
) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
December 2009
M9999-121409-D
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89809L
Ordering Information
(1)
Part Number
SY89809LTC
SY89809LTCTR
SY89809LTH
(3)
(2)
Package
Type
T32-1
T32-1
T32-1
T32-1
Operating
Range
Commercial
Commercial
Commercial
Commercial
Package Marking
SY89809LTC
SY89809LTC
SY89809LTH with Pb-Free
bar-line indicator
SY89809LTH with Pb-Free
bar-line indicator
Lead
Finish
Sn-Pb
Sn-Pb
NiPdAu
Pb-Free
NiPdAu
Pb-Free
SY89809LTHTR
(2, 3)
Notes:
1.
2.
3.
Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
Tape and Reel.
Pb-Free package is recommended for new designs.
Pin Configuration
32-Pin TQFP (T32-1)
December 2009
2
M9999-121409-D
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89809L
Pin Description
Pin Number
2, 3
Pin Name
HSTL_CLK,
/HSTL_CLK
LVPECL_CLK,
/LVPECL_CLK
CLK_SEL
OE
Type
HSTL Input
Pin Function
Differential input: This HSTL input can be selected by CLK_SEL. If it is not
used, it can be left floating. This produces a LOW at the output. If driven by an
HSTL driver, an external 50Ω to ground termination is required at the input.
Differential input: This LVPECL input can be selected by CLK_SEL. If it is not
used, it can be left floating. This produces a LOW at the output (internal 75kΩ
pull-downs).
Selected HSTL_CLK input when LOW and LVPECL_CLK output when HIGH.
11kΩ pull-up.
Single-ended input: This LVTTL input disables and enables the Q0-Q8 output
pairs. It is internally synchronized to prevent glitching of the Q0-Q8 output
pairs. It is internally connected to a 11kΩ pull-up resistor and will default to a
logic HIGH state if left open.
Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and
LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated
with 50Ω to GND. Q0-Q8 outputs are static LOW when OE = LOW. Unused
output pairs may be left floating.
Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and
LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated
with 50Ω to GND. /Q0-/Q8 outputs are static HIGH when OE = LOW. Unused
output pairs may be left floating.
Core V
CC
connected to 3.3V supply. Bypass with 0.1µF in parallel with 0.01µF
low ESR capacitors as close to V
CCI
pin as possible.
Output Buffer VCC connected to 1.8V supply. Bypass with 0.1µF in parallel
with 0.01µF low ESR capacitors as close to V
CCO
pins as possible. All V
CCO
pins should be connected together on the PCB.
Ground.
5, 6
LVPECL
Input
LVTTL Input
LVTTL Input
4
8
31, 29, 27,
23, 21, 19,
15, 13, 11
30, 28, 26,
22, 20, 18,
14, 12, 10
1
9, 16, 17,
24, 25, 32
7
Q0 – Q8
HSTL Output
/Q0 – /Q8
HSTL Output
VCCI
VCCO
VCC Core
Power
VCC Output
Power
Ground
GND
December 2009
3
M9999-121409-D
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89809L
Absolute Maximum Ratings
(1)
Supply Voltage (V
IN
) ........................................ –0.5V to V
CCI
V
CC
Pin Potential to Ground Pin
(V
CCI
, V
CCO
) ............................................ –0.5V to +4.0V
DC Output Current, Output HIGH (I
OUT
) ....................–50mA
Lead Temperature (soldering, 20sec.)....................... 260°C
Storage Temperature (T
s
) .........................–65°C to +150°C
Operating Ratings
(2)
Supply Voltage
(V
CCI
) ...................................................... +3.0V to +3.6V
(V
CCO
)..................................................... +1.6V to +2.0V
Ambient Temperature (T
A
) .............................. 0°C to +85°C
Package Thermal Resistance
TQFP (θ
JA
)
–Still-Air.......................................................50°C/W
–500lfpm .....................................................42°C/W
TQFP (θ
JC
) .........................................................20°C/W
DC Electrical Characteristics
T
A
= 0°C to +85°C, unless noted.
Power Supply
Symbol
V
CCI
V
CCO
I
CCI
Parameter
V
CC
Core
V
CC
Output
I
CC
Core
Condition
Min
3.0
1.6
Typ
3.3
1.8
115
Max
3.6
2.0
140
Units
V
V
mA
HSTL
Symbol
V
OH
V
OL
V
IH
V
IL
V
X
I
IH
I
IL
Parameter
Output HIGH Voltage
(3)
Output LOW Voltage
(3)
Input HIGH Voltage
Input LOW Voltage
Input Crossover Voltage
Input HIGH Current
Input LOW Current
Condition
Min
1.0
0.2
V
X
+0.1
–0.3
0.68
+20
Typ
Max
1.2
0.4
1.6
V
X
–0.1
0.9
–350
–500
Units
V
V
V
V
V
µA
µA
LVPECL
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
0.5
Condition
Min
V
CCI
–1.165
V
CCI
–1.810
Typ
Max
V
CCI
–0.880
V
CCI
–1.475
+150
Units
V
V
µA
µA
LVCMOS/LVTTL
Symbol
V
IH
V
IL
I
IH
I
IL
Notes:
1.
2.
3.
Exceeding the absolute maximum rating may damage the device.
The device is not guaranteed to function outside its operating rating.
Outputs loaded with 50Ω to ground.
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Condition
Min
2.0
Typ
Max
0.8
Units
V
V
µA
µA
+20
–250
–600
December 2009
4
M9999-121409-D
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89809L
AC Electrical Characteristics
(4)
T
A
= 0°C to +85°C, unless noted.
Symbol
t
PD
f
MAX
t
SKEW
t
SKPP
t
JITTER
V
PP
V
CMR
t
S
t
H
t
r
, t
f
Notes:
4.
5.
6.
7.
8.
9.
Outputs loaded with 50Ω to ground. Airflow
≥
300lfpm.
Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential
output signals.
Output swing greater than 450mV.
The within-device skew is defined as the worst-case difference between any two similar delay paths within a single device operating at the same
voltage and temperature.
The part-to-part skew is defined as the absolute worst-case difference between any two delay paths on any two devices operating at the same
voltage and temperature.
The V
PP
(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay.
Parameter
Propagation Delay
(5)
Maximum Operating Frequency
(6)
Within-Device Skew
(7)
Part-to-Part Skew
(8)
Phase Noise(RMS)
Minimum Input Swing
LVPECL_CLK
(9)
Condition
Min
825
500
Typ
1050
Max
1275
50
200
Units
ps
MHz
ps
ps
ps
mV
12kHz-20MHz @ 500MHz
See Figure 3
600
–1.5
1.0
0.5
300
0.241
1
Common Mode Range
(10)
LVPECL_CLK
OE Set-Up Time
(11)
OE Hold Time
Output Rise/Fall Time
(20% to 80%)
–0.4
V
ns
ns
650
ps
10. V
CMR
is defined as the range within which the VIH level may vary with the device still meeting the propagation delay specification. The numbers in
the table are referenced to V
CCI
. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to V
PP
(min).
11. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH-to-LOW transition ensures outputs remain disabled during the next
clock cycle.
December 2009
5
M9999-121409-D
hbwhelp@micrel.com
or (408) 955-1690
京公网安备 11010802033920号
EEWORLD
