FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50220-3E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
16 M (×8/×16) FLASH MEMORY &
× ×
4 M (×8/×16) STATIC RAM
× ×
MB84VD2118XEG-
70/85
/MB84VD2119XEG-
70/85
s
FEATURES
•
Power Supply Voltage of 2.7 V to 3.3 V
•
High Performance
85 ns maximum access time (Flash)
85 ns maximum access time (SRAM)
(Continued)
s
PRODUCT LINE UP
Flash Memory
70
Power Supply Voltage (V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
70
70
30
85
V
CC
=
3.0 V
−0.3
V
70
70
35
+0.3
V
SRAM
70
85
85
35
85
85
85
45
Note : Both V
CC
f and V
CC
s must be in recommend operation range when either part is being accessed.
s
PACKAGE
56-ball plastic FBGA
(BGA-56P-M01)
MB84VD2118XEG
-85
/MB84VD2119XEG
-85
(Continued)
•
Operating Temperature
−25°C
to +85°C
•
Package 56-pin FBGA
- FLASH MEMORY
•
Simultaneous Read/Write Operations (Dual Bank)
Multiple devices available with different bank sizes (Refer to “Pin Configuration” in “
s
PIN DESCRIPTION”)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
•
Minimum 100,000 Write/Erase Cycles
•
Sector Erase Architecture
Eight 4 K words and thirty-one 32 K words.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
•
Boot Code Sector Architecture
MB84VD2118X : Top sector
MB84VD2119X : Bottom sector
•
Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
•
Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
•
Data Polling and Toggle Bit Feature for detection of program or erase cycle completion
•
Ready-Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
•
Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
•
Low V
CC
Write Inhibit
≤
2.5 V
•
Hidden ROM (Hi-ROM) Region
64 K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
•
WP/ACC Input Pin
At V
IL
, allows protection of boot sectors, regardless of sector protection/unprotection status
(MB84VD2118XEG : SA37, SA38 MB84VD2119XEG : SA0, SA1)
At V
IH
, allows removal of boot sector protection
At V
ACC
, program time will be reduced by 40%.
•
Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
•
Please refer to “MBM29DL16XTE/BE” Datasheet in Detailed Function
- SRAM
•
Power Dissipation
Operating : 40 mA Max
Standby : 7
µA
Max
•
Power Down Features Using CE1s and CE2s
•
Data Retention Supply Voltage : 1.5 V to 3.3 V
•
CE1s and CE2s Chip Select
•
Byte Data Control : LBs (DQ
7
-DQ
0
) , UBs (DQ
15
-DQ
8
)
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
2
MB84VD2118XEG
-85
/MB84VD2119XEG
-85
s
PIN DESCRIPTION
Pin
A
17
to A
0
A
19
to A
18
, A
-1
SA
DQ
15
to DQ
0
CEf
CE1s
CE2s
OE
WE
RY/BY
UBs
LBs
CIOf
CIOs
RESET
WP/ACC
N.C.
V
SS
V
CC
f
V
CC
s
Address Inputs (Common)
Address Input (Flash)
Address Input (SRAM)
Data Inputs/Outputs (Common)
Chip Enable (Flash)
Chip Enable (SRAM)
Chip Enable (SRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Outputs (Flash) Open Drain Output
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
I/O Configulation (Flash)
CIOf
=
Vccf is Word mode (×16) , CIOf
=
Vss is Byte mode (×8)
I/O Configulation (SRAM)
CIOs
=
Vccs is Word mode (×16) , CIOs
=
Vss is Byte mode (×8)
Hardware Reset Pin/Sector Protection Unlock (Flash)
Write Protect / Acceleration (Flash)
No Internal Connection
Device Ground (Common)
Device Power Supply (Flash)
Device Power Supply (SRAM)
Function
Input/Output
I
I
I
I/O
I
I
I
I
I
O
I
I
I
I
I
I
—
Power
Power
Power
4
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