K4S283233F-M(E)E/N/I/P
1M x 32Bit x 4 Banks SDRAM in 90FBGA
FEATURES
•
•
•
•
3.0V & 3.3V power supply
LVCMOS compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (1, 2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle).
Extended Temperature Operation (-25
°C
~ 85°C).
Industial Temperature Operation (-40°C ~ 85
°C).
90Balls FBGA based on 2 pcs of 4Mx16 SDRAM( -MXXX -Pb,
-EXXX -Pb Free)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S283233F is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits,
fabricated with SAMSUNG′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable burst
lengths and programmable latencies allow the same device to be
useful for a variety of high bandwidth and high performance mem-
ory system applications.
•
•
•
•
•
•
•
•
ORDERING INFORMATION
Part No.
K4S283233F-ME/N/I/P75
K4S283233F-ME/N/I/P1H
K4S283233F-ME/N/I/P1L
K4S283233F-EE/N/I/P75
K4S283233F-EE/N/I/P1H
K4S283233F-EE/N/I/P1L
Max Freq.
133MHz(CL=3)
105MHz(CL=2)
105MHz(CL=2)
105MHz(CL=3)
*1
133MHz(CL=3)
105MHz(CL=2)
105MHz(CL=2)
105MHz(CL=3)
*1
LVCMOS
90FBGA
Pb Free
Interface Package
90FBGA
Pb
FUNCTIONAL BLOCK DIAGRAM
- M(E)E/N : Normal/Low Power, Temp : -25
°C
~ 85°C.
- M(E)I/P : Normal/Low Power, Temp : -40
°C
~ 85°C.
Note :
1. In case of 40MHz Frequency, CL1 can be supported.
I/O Control
LWE
Data Input Register
LDQM
Bank Select
1M x 32
1M x 32
1M x 32
1M x 32
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
LRAS
LCBR
Latency & Burst Length
LCKE
LRAS
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
* Samsung Electronics reserves the
right to change products or specification
without notice.
CLK
CKE
CS
RAS
CAS
WE
DQM
Rev. 1.5 Dec. 2002
K4S283233F-M(E)E/N/I/P
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
D D
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
D D
, V
DDQ
T
S T G
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
CMOS SDRAM
Unit
V
V
°C
W
mA
Notes
:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to V
SS
= 0V, T
A
= -25°C to 85°C for Extended, -40
°C
to 85°C for Industrial)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
V
D D
V
DDQ
V
I H
V
IL
V
O H
V
OL
I
LI
Min
2.7
2.7
2.0
-0.3
2.4
-
-10
Typ
3.0
3.0
3.0
0
-
-
-
Max
3.6
3.6
V
DDQ
+0.3
0.8
-
0.4
10
Unit
V
V
V
V
V
V
uA
1
2
I
O H
= -2mA
I
OL
= 2mA
3
Note
Notes
:
1. V
IH
(max) = 5.3V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with tri-state outputs.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DDQ.
CAPACITANCE
(V
D D
= 3.0V & 3.3V, T
A
= 23°C, f = 1MHz, V
REF
Pin
Clock
RAS, CAS, WE, CS, CKE, DQM
Address
D Q
0
~ DQ
31
Symbol
C
CLK
C
IN
C
ADD
C
OUT
=0.9V
±
50 mV)
Min
4.0
4.0
4.0
3.0
Max
8.0
8.0
8.0
6.5
Unit
pF
pF
pF
pF
Note
Rev. 1.5 Dec. 2002
K4S283233F-M(E)E/N/I/P
DC CHARACTERISTICS
CMOS SDRAM
Recommended operating conditions(Voltage referenced to V
SS
= 0V, T
A
= -25
°C
to 85°C for Extended, -40°C to 85
°C
for Industrial)
Parameter
Symbol
Burst length = 1
t
RC
≥
t
RC
(min)
I
O
= 0 mA
CKE
≤
V
IL
(max), t
C C
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
I H
(min), CS
≥
V
I H
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
Test Condition
-75
Operating Current
(One Bank Active)
Precharge Standby Current in
power-down mode
I
CC1
150
Version
-1H
140
-1L
130
mA
1
Unit
Note
I
C C 2
P
I
C C 2
PS
I
CC2
N
2
2
30
mA
Precharge Standby Current
in non power-down mode
CKE
≥
V
I H
(min), CLK
≤
V
IL
(max), t
CC
=
∞
I
C C 2
NS
Input signals are stable
I
C C 3
P
I
C C 3
PS
I
CC3
N
CKE
≤
V
IL
(max), t
C C
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
I H
(min), CS
≥
V
I H
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
I H
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
t
RC
≥
t
RC
(min)
CKE
≤
0.2V
-M(E)E/I
-M(E)N/P
mA
12
6
6
60
mA
Active Standby Current
in power-down mode
mA
Active Standby Current
in non power-down mode
(One Bank Active)
I
C C 3
NS
50
mA
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S283233F-M(E)E/I**
4. K4S283233F-M(E)N/P**
I
CC4
220
180
170
mA
1
I
CC5
I
CC6
250
220
2
800
210
mA
mA
uA
2
3
4
5. Unless otherwise noted, input swing IeveI is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ)
Rev. 1.5 Dec. 2002
PCB Design
京公网安备 11010802033920号
EEWORLD
