K4B2G0846D-HYH90 datasheet, PDF

Datasheet> All Categories > storage> storage> K4B2G0846D-HYH90

K4B2G0846D-HYH90: DescriptionDDR DRAM, 256MX8, 0.25ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78; Categorystorage storage; File Size2MB，64 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/; Environmental Compliance

Download Datasheet Parametric Compare View All

K4B2G0846D-HYH90 Overview

DDR DRAM, 256MX8, 0.25ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78

K4B2G0846D-HYH90 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	TFBGA, BGA78,9X13,32
Contacts	78
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	MULTI BANK PAGE BURST
Maximum access time	0.25 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	667 MHz
I/O type	COMMON
interleaved burst length	8
JESD-30 code	R-PBGA-B78
length	11 mm
memory density	2147483648 bit
Memory IC Type	DDR DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	78
word count	268435456 words
character code	256000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	256MX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA78,9X13,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.35 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	8
Maximum standby current	0.01 A
Maximum slew rate	0.12 mA
Maximum supply voltage (Vsup)	1.45 V
Minimum supply voltage (Vsup)	1.283 V
Nominal supply voltage (Vsup)	1.35 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.5 mm

Preview

Download Datasheet

View All

Rev. 1.04, Aug. 2011

K4B2G0446D

K4B2G0846D

2Gb D-die DDR3L SDRAM

78FBGA with Lead-Free & Halogen-Free

(RoHS compliant)

1.35V

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND

SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed

herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung

Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property

right is granted by one party to the other party under this document, by implication, estoppel or other-

wise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or

similar applications where product failure could result in loss of life or personal or physical harm, or any

military or defense application, or any governmental procurement to which special terms or provisions

may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

ⓒ

-1-

K4B2G0446D

K4B2G0846D

datasheet

Rev. 1.04

DDR3L SDRAM

Table Of Contents

2Gb D-die DDR3L SDRAM

1. Ordering Information ..................................................................................................................................................... 5

2. Key Features................................................................................................................................................................. 5

3. Package pinout/Mechanical Dimension & Addressing.................................................................................................. 6

3.1 x4 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 6

3.2 x8 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 7

3.3 FBGA Package Dimension (x4/x8) .......................................................................................................................... 8

4. Input/Output Functional Description.............................................................................................................................. 9

5. DDR3 SDRAM Addressing ........................................................................................................................................... 10

6. Absolute Maximum Ratings .......................................................................................................................................... 11

6.1 Absolute Maximum DC Ratings............................................................................................................................... 11

6.2 DRAM Component Operating Temperature Range ................................................................................................ 11

7. AC & DC Operating Conditions..................................................................................................................................... 11

7.1 Recommended DC operating Conditions ................................................................................................................ 11

8. AC & DC Input Measurement Levels ............................................................................................................................ 12

8.1 AC & DC Logic input levels for single-ended signals .............................................................................................. 12

8.2 V

REF

Tolerances...................................................................................................................................................... 14

8.3 AC & DC Logic Input Levels for Differential Signals ................................................................................................ 15

8.3.1. Differential signals definition ............................................................................................................................ 15

8.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) .................................................. 15

8.3.3. Single-ended requirements for differential signals ........................................................................................... 17

8.4 Differential Input Cross Point Voltage...................................................................................................................... 18

8.5 Slew rate definition for Differential Input Signals ..................................................................................................... 19

8.6 Slew rate definitions for Differential Input Signals ................................................................................................... 19

9. AC & DC Output Measurement Levels ......................................................................................................................... 19

9.1 Single-ended AC & DC Output Levels..................................................................................................................... 19

9.2 Differential AC & DC Output Levels......................................................................................................................... 19

9.3 Single-ended Output Slew Rate .............................................................................................................................. 20

9.4 Differential Output Slew Rate .................................................................................................................................. 21

9.5 Reference Load for AC Timing and Output Slew Rate ............................................................................................ 21

9.6 Overshoot/Undershoot Specification ....................................................................................................................... 22

9.6.1. Address and Control Overshoot and Undershoot specifications...................................................................... 22

9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................... 23

9.7 34ohm Output Driver DC Electrical Characteristics................................................................................................. 23

9.7.1. Output Drive Temperature and Voltage Sensitivity .......................................................................................... 25

9.8 On-Die Termination (ODT) Levels and I-V Characteristics ..................................................................................... 25

9.8.1. ODT DC Electrical Characteristics ................................................................................................................... 26

9.8.2. ODT Temperature and Voltage sensitivity ....................................................................................................... 28

9.9 ODT Timing Definitions ........................................................................................................................................... 29

9.9.1. Test Load for ODT Timings.............................................................................................................................. 29

9.9.2. ODT Timing Definitions .................................................................................................................................... 29

10. IDD Current Measure Method ..................................................................................................................................... 32

10.1 IDD Measurement Conditions ............................................................................................................................... 32

11. 2Gb DDR3 SDRAM D-die IDD Specification Table .................................................................................................... 41

12. Input/Output Capacitance ........................................................................................................................................... 42

13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600 ...................................................................... 43

13.1 Clock Specification ................................................................................................................................................ 43

13.1.1. Definition for tCK(avg).................................................................................................................................... 43

13.1.2. Definition for tCK(abs).................................................................................................................................... 43

13.1.3. Definition for tCH(avg) and tCL(avg) .............................................................................................................. 43

13.1.4. Definition for note for tJIT(per), tJIT(per, Ick) ................................................................................................. 43

13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) ................................................................................................................. 43

13.1.6. Definition for tERR(nper)................................................................................................................................ 43

13.2 Refresh Parameters by Device Density................................................................................................................. 44

13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 44

13.3.1. Speed Bin Table Notes .................................................................................................................................. 47

-3-

K4B2G0846D-HYH90 Related Products

	K4B2G0846D-HYH90	K4B2G0446D-HYK00	K4B2G0846D-HYF80	K4B2G0446D-HYH90	K4B2G0446D-HYF80	K4B2G0846D-HYK00
Description	DDR DRAM, 256MX8, 0.25ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	DDR DRAM, 512MX4, 0.225ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	DDR DRAM, 256MX8, 0.3ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	DDR DRAM, 512MX4, 0.25ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	DDR DRAM, 512MX4, 0.3ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	DDR DRAM, 256MX8, 0.225ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to
Maker	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	TFBGA, BGA78,9X13,32	TFBGA, BGA78,9X13,32	TFBGA, BGA78,9X13,32	TFBGA, BGA78,9X13,32	TFBGA, BGA78,9X13,32	TFBGA, BGA78,9X13,32
Contacts	78	78	78	78	78	78
Reach Compliance Code	compliant	compliant	compliant	compliant	compli	compli
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST
Maximum access time	0.25 ns	0.225 ns	0.3 ns	0.25 ns	0.3 ns	0.225 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	667 MHz	800 MHz	533 MHz	667 MHz	533 MHz	800 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
interleaved burst length	8	8	8	8	8	8
JESD-30 code	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78
length	11 mm	11 mm	11 mm	11 mm	11 mm	11 mm
memory density	2147483648 bit	2147483648 bit	2147483648 bit	2147483648 bit	2147483648 bi	2147483648 bi
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	8	4	8	4	4	8
Number of functions	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1
Number of terminals	78	78	78	78	78	78
word count	268435456 words	536870912 words	268435456 words	536870912 words	536870912 words	268435456 words
character code	256000000	512000000	256000000	512000000	512000000	256000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
organize	256MX8	512MX4	256MX8	512MX4	512MX4	256MX8
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
Encapsulate equivalent code	BGA78,9X13,32	BGA78,9X13,32	BGA78,9X13,32	BGA78,9X13,32	BGA78,9X13,32	BGA78,9X13,32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192	8192	8192
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES	YES	YES	YES
Continuous burst length	8	8	8	8	8	8
Maximum standby current	0.01 A	0.01 A	0.01 A	0.01 A	0.01 A	0.01 A
Maximum slew rate	0.12 mA	0.13 mA	0.11 mA	0.125 mA	0.11 mA	0.125 mA
Maximum supply voltage (Vsup)	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V
Minimum supply voltage (Vsup)	1.283 V	1.283 V	1.283 V	1.283 V	1.283 V	1.283 V
Nominal supply voltage (Vsup)	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	7.5 mm	7.5 mm	7.5 mm	7.5 mm	7.5 mm	7.5 mm

Recommended Resources

T-121 temperature sensor constitutes temperature control circuit diagram

Square wave generator circuit

AC and DC input automatic switching circuit diagram

555 kitchen ventilation fan automatic switch circuit

Low-pass or high-pass filter circuit using BUF-03

Use welding transformer to heat and dry motor winding circuit

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components