Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33892
Rev 1.0, 03/2004
Preliminary Information
Quad Intelligent High-Side Switch
(Dual 10 mΩ and Dual 35 mΩ)
The 33892 is one in a family of devices designed for low-voltage automotive
and industrial lighting and motor control applications. Its four low R
DS(ON)
MOSFETs (two 10 mΩ, two 35 mΩ) can control the high sides of four separate
resistive or inductive loads or serve as high-side switches for a pair of DC
motors.
33892
QUAD INTELLIGENT
HIGH-SIDE SWITCH
Freescale Semiconductor, Inc...
Programming, control, and diagnostics are accomplished using a 16-bit SPI
interface. Additionally, each output has its own parallel input for PWM control
if desired. The 33892 allows the user to program via the SPI the fault current
trip levels and duration of acceptable lamp inrush or motor stall intervals. Such
programmability allows tight control of fault currents and can protect wiring
harnesses and circuit boards as well as loads.
The 33892 is packaged in a power-enhanced 10 x 10 nonleaded Power
QFN package with exposed tabs.
Features
• Dual 10 mΩ and Dual 35 mΩ High-Side Switches
• Operating Voltage Range of 6.0 V to 27 V with Standby Current < 5.0
µA
• SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time,
Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog
Timeout, Slew Rates, and Fault Status Reporting
• SPI Status Reporting of Overcurrent, Open and Shorted Loads,
Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe
Terminal Status, and Program Status
• Analog Current Feedback with Selectable Ratio
• Enhanced 16 V Reverse Polarity V
PWR
Protection
Simplified Application Diagram
VPWR
VDD
VDD
VDD
VPWR
PNC SUFFIX
CASE 1558-02
24-TERMINAL PQFN
ORDERING INFORMATION
Device
PC33892PNC/R2
Temperature
Range (T
A
)
-40
°
C to 125
°
C
Package
24 PQFN
33892 Simplified Application Diagram
33892
VDD
WAKE
SO
SCLK
CS
SI
MCU
I/O
I/O
I/O
I/O
I/O
I/O
A/D
GND
SI
SCLK
CS
SO
RST
FS
IN0
IN1
IN2
IN3
CSNS
FSI
GND
HS3
LOAD 3
HS2
LOAD 2
HS1
LOAD 1
VPWR
HS0
LOAD 0
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
© Motorola, Inc. 2004
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
V
DD
V
PWR
Internal
Regulator
Over/Undervoltage
Protection
Selectable Slew
Rate Gate Drive
Freescale Semiconductor, Inc...
CS
SCLK
SO
SI
RST
WAKE
FS
IN0
IN1
IN2
IN3
SPI
3.0 MHz
Selectable Current Limit
HS[0:1]: 100 A or 70 A
HS[2:3]: 50 A or 35 A
Logic
Selectable Current
Detection Time
0.15 ms–620 ms
Open
Load
Detection
Overtemperature
Detection
Selectable Over-
current Detection
HS[0:1]: 4.8 A–18.2 A
HS[2:3]: 2.4 A–9.1 A
HS0
HS0
HS1
Programmable
Watchdog
310 ms–2500 ms
HS1
HS2
HS2
FSI
HS3
Selectable Output Current
Recopy (Analog MUX)
HS[0:1]: 1/13000 or 1/40000
HS[2:3]: 1/6500 or 1/20000
HS3
GND
CSNS
Figure 1. 33892 Simplified Internal Block Diagram
33892
2
MOTOROLA ANALOG
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RST
IN3
3
IN2
V
DD
SO
GND
11
12
13
10 9
8
7
6 5
4
2 1
IN1
CS
FS
SI
Transparent Top View of Package
WAKE
SCLK
GND
24
23
22
IN0
CSNS
FSI
GND
14
HS3
15
21
HS2
16
Freescale Semiconductor, Inc...
V
PWR
HS1
17
18
HS1
19
HS0
20
HS0
TERMINAL FUNCTION DESCRIPTION
Terminal
1
2
3
24
4
Terminal Name
IN1
IN2
IN3
IN0
Formal Name
Serial Inputs
Definition
The IN0–IN3 high-side input terminals are used to directly control HS0–HS3 high-side
output terminals, respectively. An SPI register determines if each input is activated or
if the input logic state is ORed or ANDed with the SPI instruction. These terminals are
to be driven with 5.0 V CMOS levels, and they have an internal active pull-down current
source.
This terminal is an open drain configured output requiring an external pull-up resistor
to V
DD
for fault reporting. If a device fault condition is detected, this terminal is active
LOW. Specific device diagnostic faults are reported via the SPI SO terminal.
This terminal is an input that controls the device mode and watchdog timeout feature
if enabled. An internal clamp protects this terminal from high damaging voltages when
the output is current limited with an external resistor. This input has an internal passive
pull-down.
These terminals are the ground for the logic and analog circuitry of the device.
This terminal is an input used to initialize the device configuration and fault registers,
as well as place the device in a low-current sleep mode. The terminal also starts the
watchdog timer when transitioning from logic [0] to logic [1]. This terminal should not
be allowed to be logic [1] until V
DD
is in regulation. This terminal has an internal passive
pull-down.
This terminal is an input terminal connected to a chip select output of a master
microcontroller (MCU). The MCU determines which device is addressed (selected) to
receive data by pulling the
CS
terminal of the selected device logic LOW, thereby
enabling SPI communication with the device. Other
unselected
devices on the serial
link having their
CS
terminals pulled up logic HIGH disregard the SPI communication
data sent. This terminal has an internal active pull-up current source and requires
CMOS logic levels.
This terminal is an input terminal connected to the MCU providing the required bit shift
clock for SPI communication. It transitions one time per bit transferred at an operating
frequency, f
SPI
, defined by the communication interface. The 50 percent duty cycle
CMOS level serial clock signal is idle between command transfers. The signal is used
to shift data into and out-of the device. This terminal has an internal active pull-down.
FS
Fault Status
(Active Low)
5
WAKE
Wake
6, 13, 15
7
GND
RST
Ground
Reset
8
CS
Chip Select
(Active Low)
9
SCLK
Serial Clock
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TERMINAL FUNCTION DESCRIPTION (continued)
Terminal
10
Terminal Name
SI
Formal Name
Serial Input
Definition
This terminal is a command data input terminal connected to the SPI Serial Data
Output of the MCU or to the SO terminal of the previous device of a daisy chain of
devices. The input requires CMOS logic level signals and incorporates an internal
active pull-down. Device control is facilitated by the input's receiving the MSB first of a
serial 8-bit control command. The MCU ensures data is available upon the falling edge
of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit
command into the internal command shift register. This terminal has an internal active
pull-down.
This terminal is an external voltage input terminal used to supply power to the SPI
circuit. In the event V
DD
is lost, an internal supply provides power to a portion of the
logic, ensuring limited functionality of the device.
This terminal is an output terminal connected to the SPI Serial Data Input terminal of
the MCU or to the SI terminal of the next device of a daisy chain of devices. This output
will remain tri-stated (high-impedance OFF condition) so long as the
CS
terminal of the
device is logic HIGH. SO is only active when the CS terminal of the device is asserted
logic LOW. The generated SO output signals are CMOS logic levels. SO output data
is available on the falling edge of SCLK and transitions immediately on the rising edge
of SCLK.
This terminal connects to the positive power supply and is the source of operational
power for the device. The V
PWR
contact is the backside surface mount tab of the
package.
Protected 35 mΩ high-side power output terminals to the load.
Protected 10 mΩ high-side power output terminals to the load.
The value of the resistance connected between this terminal and ground determines
the state of the outputs after a Watchdog timeout occurs. Depending on the resistance
value, either all outputs are OFF or the output HSO only is ON. If the FSI terminal is
left to float up to a logic [1] level, then the outputs HS0 and HS2 will turn ON when in
the Fail-Safe state. When the FSI terminal is connected to GND, the Watchdog circuit
and Fail-Safe operation are disabled. This terminal incorporates an active internal pull-
up.
The Current Sense terminal sources a current proportional to the designated HS0–
HS3 output. That current is fed into a ground referenced resistor and its voltage is
monitored by an MCU's A/D. The channel to be monitored is selected via the SPI. This
terminal can be tri-stated through SPI.
11
V
DD
Digital Drain Voltage
(Power)
12
SO
Serial Output
Freescale Semiconductor, Inc...
16
V
PWR
Positive Power Supply
14
21
17, 18
19, 20
22
HS3
HS2
HS1 (Note 1)
HS0 (Note 2)
FSI
High-Side Outputs
High-Side Outputs
Fail-Safe Input
23
CSNS
Output Current
Monitoring
Notes
1. HS1 output (17 and 18) must be connected externally on the PCB as close as possible to the terminals.
2. HS0 output (19 and 20) must be connected externally on the PCB as close as possible to the terminals.
33892
4
MOTOROLA ANALOG
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Operating Voltage Range
Steady-State
V
DD
Supply Voltage
Input/Output Voltage (Note 3)
V
DD
V
IN[0:3]
,
RST
, FSI,
CSNS, SI, SCLK,
CS
,
FS
V
SO
I
CL(WAKE)
I
CL(CSNS)
I
HS0,
I
HS1
I
HS2,
I
HS3
E
CL0,
E
CL1
E
CL2,
E
CL3
T
STG
T
A
T
J
R
θ
JC
R
θ
JA
V
ESD1
V
ESD2
T
SOLDER
Symbol
V
PWR(SS)
-16 to 41
0 to 5.5
-0.3 to 7.0
V
V
Value
Unit
V
SO Output Voltage (Note 3)
WAKE Input Clamp Current
-0.3 to V
DD
+0.3
2.5
10
25
12
TBD
TBD
-55 to 150
-40 to 125
-40 to 150
V
mA
mA
A
A
J
J
Freescale Semiconductor, Inc...
CSNS Input Clamp Current
Output Current (Note 4)
Output Current (Note 4)
Output Clamp Energy (Note 5)
Output Clamp Energy (Note 5)
Storage Temperature
Operating Ambient Temperature
Operating Junction Temperature
Thermal Resistance
Junction to Case
Junction to Ambient
ESD Voltage
Human Body Model (Note 6)
Machine Model (Note 7)
Terminal Soldering Temperature (Note 8)
°
C
°
C
°
C
°
C/W
<1.0
TBD
V
±2000
±200
240
°
C
Notes
3. Exceeding voltage limits on IN[0:3],
RST
, FSI, CSNS, SI, SO, SCLK,
CS
, or
FS
terminals may cause a malfunction or permanent damage to
the device.
4. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current
using package thermal resistance is required.
5. Active clamp energy using single-pulse method (L = 16 mH, R
L
= 0
Ω,
V
PWR
= 12 V, T
J
= 150
°
C).
6.
7.
8.
ESD1 testing is performed in accordance with the Human Body Model (C
ZAP
= 100 pF, R
ZAP
= 1500
Ω).
ESD2 testing is performed in accordance with the Machine Model (C
ZAP
= 200 pF, R
ZAP
= 0
Ω)
and in accordance with the system module
specification with a capacitor > 0.01
µF
connected from high-side outputs to GND.
Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
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33892
5
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