Freescale Semiconductor
Technical Data
Document Number: MC33882
Rev. 6.0, 6/2009
Six-Output Low-Side Switch
with SPI and Parallel Input
Control
The 33882 is a smart six-output low-side switch able to control
system loads up to 1.0 A. The six outputs can be controlled via both
serial peripheral interface (SPI) and parallel input control, making the
device attractive for fault-tolerant system applications. There are two
additional 30 mA low-side switches with SPI diagnostic reporting
(with parallel input control only).
The 33882 is designed to interface directly with industry-standard
microcontrollers via SPI to control both inductive and incandescent
loads. Outputs are configured as open-drain power MOSFETs
incorporating internal dynamic clamping and current limiting. The
device has multiple monitoring and protection features, including low
standby current, fault status reporting, internal 52 V clamp on each
output, output-specific diagnostics, and protective shutdown. In
addition, it has a mode select pin affording a dual means of input
control.
Features
•
•
•
•
•
•
•
•
•
Outputs Clamped for Switching Inductive Loads
Very Low Operational Bias Currents (< 2.0 mA)
CMOS Input Logic Compatible with 5.0 V Logic Levels
Load Dump Robust (60 V Transient at V
PWR
on OUT0 – OUT5)
Daisy Chain Operation of Multiple Devices Possible
Switch Outputs Can Be Paralleled for Higher Currents
R
DS(ON)
of 0.4
Ω
per Output (25°C) at 13 V V
PWR
SPI Operation Guaranteed to 2.0 MHz
Pb-Free Packaging Designated by Suffix Codes VW and EP
VDD
33882
SIX-OUTPUT LOW-SIDE SWITCH
DH SUFFIX
VW SUFFIX (PB-FREE)
98ASH70329A
30-PIN HSOP
FC SUFFIX
EP SUFFIX (PB-FREE)
98ARH99032A
32-PIN QFN
ORDERING INFORMATION
Device
MC33882DH/R2
MC33882VW/R2
MC33882FC/R2
MC33882EP/R2
-40°C to 125°C
32 QFN
Temperature
Range (T
A
)
Package
30 HSOP
VPWR
33882
VPWR
VDD
CS
MCU
SCLK
SI
SO
IN0
IN1
IN2
Optional Parallel
Control of
Outputs 0 through 7
IN3
IN4
IN5
IN6
IN7
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
IN0 & IN1
IN2 & IN3
IN4 & IN5
MODE
GND
Optional Control
of Paired Outputs
Low-Power
LED
Outputs
High-Power
Outputs
Figure 1. 33882 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006 -2009. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
1 (V
PWR
)
12 (SI)
DQ
C
DQ
C
DQ
C
DQ
C
DQ
C
DQ
C
DQ
C
DQ
C
On Open
16 (V
DD
)
Undervoltage
Shutdown
Internal
Bias
V DD
Overvoltage
Shutdown
3 (MODE)
18 (IN7)
29 (IN6)
27 (IN5)
24 (IN4)
28 (IN4 & IN5)
21 (IN3)
9 (IN2)
19 (IN2 & IN3)
Detect
Logic
Gate 7
Gate 6
Gate 5
Gate 4
Gate 3
Gate 2
Gate 0
OUT6
and OUT7
Unclamped
Low
Power
17
(OUT7)
30 (OUT6)
26 (OUT5)
OUT1
to OUT5
High
Power
23 (OUT4)
20 (OUT3)
10 (OUT2)
7 (OUT1)
5 (OUT0)
52 V
Gate 0
6 (IN1)
4 (IN0)
2 (IN0 & IN1)
Serial In
13 (SCLK)
0
1
2
3
4
5
6
7
SO Fault Latch/Shift Register
Output 0 Status
Output Status
1 through 7
Serial Out
V REF
I LIM
V DD
OFF/ON
Open
Load
Detect
V OF (th)
3.0 V
I O(OFF)
40
μA
+-
GND (Heat Sink)
-+
14 (CS)
Tri-state
15 (SO)
Shift
Enable
3.0 A
Load
Short
Detect
-+
Note
Pin numbers shown in this figure are applicable only to the 30-lead HSOP package.
Figure 2. 33882 Simplified Internal Block Diagram
33882
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
V
PWR
IN0 & IN1
MODE
IN0
OUT0
IN1
OUT1
NC
IN2
OUT2
NC
SI
SCLK
CS
SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
HEAT
SINK
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OUT6
IN6
IN4 & IN5
IN5
OUT5
NC
IN4
OUT4
NC
IN3
OUT3
IN2 & IN3
IN7
OUT7
V
DD
Figure 3. HSOP Pin Connections
Table 1. HSOP Pin Function Description
Pin
1
2
19
28
Pin Name
V
PWR
IN0 & IN1
IN2 & IN3
IN4 & IN5
Formal Name
Load Supply Voltage
Input 0 & Input 1
Input 2 & Input 3
Input 4 & Input 5
Definition
This pin is connected to battery voltage. A decoupling cap is required from V
PWR
to
ground.
These input pins control two output channels each when the
MODE
pin is pulled high.
These pins may be connected to pulse width modulated (PWM) outputs of the control
IC while the
MODE
pin is high. The states of these pins are ignored during normal
operation (
MODE
pin low) and override the normal inputs (serial or parallel) when the
MODE
pin is high. These pins have internal active 25
μA
pull-downs.
The
MODE
pin is connected to the
MODE
pin of the control IC. This pin has an internal
active 25
μA
pull-up.
These are parallel control input pins. These pins have internal 25
μA
active pull-
downs.
3
4
6
9
18
21
24
27
29
5
7
10
17
20
23
26
30
8, 11, 22, 25
12
MODE
IN0
IN1
IN2
IN7
IN3
IN4
IN5
IN6
OUT0
OUT1
OUT2
OUT7
OUT3
OUT4
OUT5
OUT6
NC
SI
Mode Select
Input 0 – Input7
Output 0 – Output7
Each pin is one channel's drain, sinking current for the respective load.
No Connect
Serial Input
Not connected.
The Serial Input pin is connected to the SPI Serial Data Output pin of the control IC
from where it receives output command data. This input has an internal active 25
μA
pull-down and requires CMOS logic levels.
33882
GND
3
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
Table 1. HSOP Pin Function Description (continued)
Pin
13
Pin Name
SCLK
Formal Name
Serial Clock
Definition
The SCLK pin of the control IC is a bit (shift) clock for the SPI port. It transitions one
time per bit transferred when in operation. It is idle between command transfers. It is
50% duty cycle, and has CMOS levels.
This pin is connected to a chip select output of the control IC. This input has an
internal active 25
μA
pull-up and requires CMOS logic levels.
This pin is connected to the SPI Serial Data Input pin of the control IC or to the SI pin
of the next device in a daisy chain. This output will remain tri-stated unless the device
is selected by a low
CS
pin or the
MODE
pin goes low. The output signal generated
will have CMOS logic levels and the output data will transition on the falling edges of
SCLK. The serial output data provides fault information for each output and is
returned MSB first when the device is addressed.
This pin is connected to the 5.0 V power supply of the system. A decoupling
capacitor is required from V
DD
to ground.
The exposed pad on this package provides the circuit ground connection for this IC.
Ground continuity is required for the outputs to turn on.
14
15
CS
SO
Chip Select
Serial Output
16
Heat Sink
(exposed pad)
V
DD
GND
Logic Supply Voltage
Ground
33882
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
IN5
IN4
IN3
32
31
30
29
28
27
26
IN4 & IN5
IN6
OUT6
GND
GND
V
PWR
IN0 & IN1
MODE
1
2
3
4
5
6
7
8
25
IN7
24
23
22
21
20
19
18
17
Transparent Top View of Package
IN2 & IN3
OUT5
OUT4
OUT3
OUT7
V
DD
GND
GND
GND
GND
SO
CS
10
12
13
14
15
OUT0
OUT1
OUT2
Figure 4. QFN Pin Connections
Table 2. QFN Pin Function Description
Pin
7
26
1
Pin Name
IN0 & IN1
IN2 & IN3
IN4 & IN5
Formal Name
Input 0 & Input 1
Input 2 & Input 3
Input 4 & Input 5
Definition
These input pins control two output channels each when the
MODE
pin is pulled high.
These pins may be connected to pulse width modulated (PWM) outputs of the control
IC while the
MODE
pin is high. The states of these pins are ignored during normal
operation (
MODE
pin low) and override the normal inputs (serial or parallel) when the
MODE
pin is high. These pins have internal active 25
μA
pull-downs.
These are parallel input pins. These pins have internal 25
μA
active pull-downs.
2
9
11
13
25
28
30
32
3
10
12
14
24
27
29
31
4, 5, 19 – 22
6
8
15
IN6
IN0
IN1
IN2
IN7
IN3
IN4
IN5
OUT6
OUT0
OUT1
OUT2
OUT7
OUT3
OUT4
OUT5
GND
V
PWR
MODE
SI
Input 0 – Input 7
Output 0 – Output 7
Each pin is one channel's drain, sinking current for the respective load.
Ground
Load Supply Voltage
Mode Select
Serial Input
Ground continuity is required for the outputs to turn on.
This pin is connected to battery voltage. A decoupling capacitor is required from
V
PWR
to ground.
The
MODE
pin is connected to the
MODE
pin of the control IC. This pin has an internal
active 25
μA
pull-up.
The Serial Input pin is connected to the SPI Serial Data Output pin of the control IC
from where it receives output command data. This input has an internal active 25
μA
pull-down and requires CMOS logic levels.
SCLK
IN0
IN1
IN2
SI
16
11
9
33882
Analog Integrated Circuit Device Data
Freescale Semiconductor
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