B9688AYB datasheet, PDF - EEWORLD Datasheet

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B9688AYB: DescriptionLow Skew Clock Driver, 18 True Output(s), 0 Inverted Output(s), PDSO48, SSOP-48; Categorylogic logic; File Size54KB，10 Pages; ManufacturerCypress Semiconductor

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B9688AYB Overview

Low Skew Clock Driver, 18 True Output(s), 0 Inverted Output(s), PDSO48, SSOP-48

B9688AYB Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	SSOP
package instruction	SSOP, SSOP48,.4
Contacts	48
Reach Compliance Code	compliant
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G48
JESD-609 code	e0
length	15.875 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	48
Actual output times	18
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Encapsulate equivalent code	SSOP48,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	220
power supply	3.3 V
Prop。Delay @ Nom-Sup	5 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.25 ns
Maximum seat height	2.794 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.5 mm
minfmax	100 MHz

B9688AYB Preview

B9688

SMBUS System Clock Buffer

Product Features

18 output buffer for high clock fanout applications

Each output can be disabled through SMBUS for

reductions of EMI/power consumption

3.3 volts operation

Output frequency range 10 Mhz to 100 MHz

< 250ps skew between output clocks

48-pin SSOP package

Single Clock Enable pin for testability

Product Description

The B9688 is a high fanout system clock buffer. Loads

of up to 30 pF are supported. One of the chief

applications of this component is where long traces are

used to transport clocks from their generating devices

to their loads. The creation of EMI and the degradation

of waveform rise and fall times are greatly reduced by

running a single reference clock trace to this device and

then using it to regenerate the clock that drives shorter

traces. Using these devices, the EMI is therefore

minimized, and board real estate is saved.

Block Diagram

VDD

CLK[1:2]

VDD

CLK[3:4]

REFIN

VDD

CLK[5:6]

VDD

CLK[7:8]

VDD

CLK[9:10]

VDD

CLK[11:12]

SDATA

SCLK

VDD

Pin Configuration

IMIB9688

VDD

CLK1

CLK2

VSS

VDD

CLK3

CLK4

VSS

REFIN

CLK[13:14]

VDD

CLK[15:16]

VDD

CLK[17,18]

VDD

CLK18

CLK17

VSS

VDD

CLK16

CLK15

VSS

VDD

CLK14

CLK13

VSS

VDD

CLK12

CLK11

VSS

VDD

CLK10

VSS

SCLOCK

Control

Logic

VDD

CLK5

CLK6

VSS

VDD

CLK7

CLK8

VSS

VDD

CLK9

VSS

VDD

SDATA

Cypress Semiconductor Corporation

525 Los Coches St.

Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571

http://www.cypress.com

Document#: 38-07075 Rev. **

05/09/01

Page 1 of 10

APPROVED PRODUCT

B9688

SMBUS System Clock Buffer

Pin Description

No.

4,5,

8,9,13,14,

17,18,21,

28, 31, 32,

35,36,40,

41,44,45

Name

REFIN

CLK(1:18)

PWR

VDD

I/O

TYPE

PAD

BUF1

Description

This pin is connected to the input reference clock. This clock

must be in the range of 10.0 to 100.0 Mhz.

Low skew output clock

PAD

6, 10, 15,

19, 22, 30,

34, 39, 43

3, 7, 12,

16, 20, 33,

37, 42, 46

23, 29

26, 27

SDATA

SDCLK

Vss

I/O

PWR

PAD

Buffer Output Enable pin. When driven to a logic low level this

pin is used to place all output clocks (CLK1: 18) in a tri state

condition. This feature facilitates in production board level

testing to be easily implemented for the clocks that this device

produces. Has internal pull-up resistor.

Serial data of SMBUS 2-wire control interface. Has internal pull-

up resistor.

Serial clock of SMBUS 2-wire control interface. Has internal

pull-up resistor.

Ground pins for clock output buffers. These pins must be

returned to the same potential to reduce output clock skew.

Power for output clock buffers.

Vdd

PWR

Vdd

Vss

PWR

Power for core logic.

Ground supply pins for internal core logic pins.

Cypress Semiconductor Corporation

525 Los Coches St.

Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571

http://www.cypress.com

Document#: 38-07075 Rev. **

05/09/01

Page 2 of 10

APPROVED PRODUCT

B9688

SMBUS System Clock Buffer

2-Wire SMBUS Control Interface

The 2-wire control interface implements a write only slave interface. The device cannot be read back. Sub addressing is

not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control

interface allows each clock output to be individually enabled or disabled.

During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK

is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the

start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer

cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a

transfer cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first.

The device will respond to writes to 10 bytes (max) of data to address

by generating the acknowledge (low) signal on

the SDATA wire following reception of each byte. The device will not respond to any other control interface conditions.

Previously set control registers are retained.

Serial Control Registers

NOTE:

The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true

power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated.

Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:

1) “Command

Code

“ byte, and

2) “Byte

Count”

byte.

Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged.

After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1,

Byte 2...) will be valid and acknowledged.

Byte 0: Function Select Register

(1 = enable, 0 = Stopped, Default = FF)

Bit

@Pup

Pin#

Description

CLK8 (Active = 1, Forced low = 0)

CLK7 (Active = 1, Forced low = 0)

CLK6 (Active = 1, Forced low = 0)

CLK5 (Active = 1, Forced low = 0)

CLK4 (Active = 1, Forced low = 0)

CLK3 (Active = 1, Forced low = 0)

CLK2 (Active = 1, Forced low = 0)

CLK1 (Active = 1, Forced low = 0)

Cypress Semiconductor Corporation

525 Los Coches St.

Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571

http://www.cypress.com

Document#: 38-07075 Rev. **

9/15/2000

Page 3 of 10

APPROVED PRODUCT

B9688

SMBUS System Clock Buffer

Byte 1: Clock Register

(1 = enable, 0 = Stopped, Default = FF)

Bit

@Pup

Pin#

Description

CLK18 (Active = 1, Forced low = 0)

CLK17(Active = 1, Forced low = 0)

CLK16 (Active = 1, Forced low = 0)

CLK15 (Active = 1, Forced low = 0)

CLK14 (Active = 1, Forced low = 0)

CLK13(Active = 1, Forced low = 0)

CLK12 (Active = 1, Forced low = 0)

CLK11 (Active = 1, Forced low = 0)

Byte 2: Clock Register

(1 = enable, 0 = Stopped, Default = C0)

Bit

@Pup

Pin#

Description

CLK10 (Active = 1, Forced low = 0)

CLK9 (Active = 1, Forced low = 0)

Not Used

Maximum Ratings

This device contains circuitry to protect the inputs

against damage due to high static voltages or electric

Voltage Relative to VSS:

Voltage Relative to VDD:

Storage Temperature:

Operating Temperature:

Maximum Power Supply:

-0.3V

0.3V

-65ºC to + 150ºC

0ºC to +70ºC

field; however, precautions should be taken to avoid

application of any voltage higher than the maximum

rated voltages to this circuit. For proper operation, Vin

and Vout should be constrained to the range:

VSS<(Vin or Vout)<VDD

Unused inputs must always be tied to an appropriate

logic voltage level (either VSS or VDD).

Cypress Semiconductor Corporation

525 Los Coches St.

Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571

http://www.cypress.com

Document#: 38-07075 Rev. **

9/15/2000

Page 4 of 10

APPROVED PRODUCT

B9688

SMBUS System Clock Buffer

DC Parameters

Characteristic

Input Low Voltage (OE)

Input High Voltage (OE)

Input Low Current

Input High Current

Input Low Voltage (SMBUS)

Input High Voltage

(SMBUS)

Tri-State leakage Current

Dynamic Supply Current

Static Supply Current

Input pin capacitance

Pin Inductance

Output Capacitance

Symbol

VIL

VIH

IIL

IIH

VIL

isc

VIH

isc

Ioz

Idd

100

Isdd

Cin

Lpin

Cout

2.2

Min

2.0

-66

Typ

Max

0.8

1.0

160

220

Units

Vdc

µA

Vdc

µA

Input frequency = 66 MHz - All outputs

on and at 30 pF load

Input frequency 100 MHz - All outputs on

and at 30 pF load

All outputs disabled no input clock

Conditions

VDD = 3.3V

±5%,

, TA = 0ºC to +70ºC

AC Parameters

Characteristic

Output Duty Cycle

Buffer out/out Skew All

Buffer Outputs

Buffer input to output Skew

Jitter Cycle to Cycle*

Jitter Absolute (Peak to

Peak)*

Symbol

tSKEW

tDLY

TJCC

TJabs

Min

2.0

Typ

Max

250

5.0

100

150

Units

@ 30 pF loading

Conditions

Measured at 1.5V (50/50 in)

35 pF Load Measured at 1.5V

VDD = 3.3V

±5%,

, TA = 0ºC to +70ºC

*This jitter is additive to the input clock’s jitter.

Cypress Semiconductor Corporation

525 Los Coches St.

Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571

http://www.cypress.com

Document#: 38-07075 Rev. **

9/15/2000

Page 5 of 10

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